Multi-level inverter

ABSTRACT

Various examples are directed to systems and methods for a multi-level inverter to convert direct current (DC) to alternating current (AC). The inverter may comprise first, second and third capacitors electrically coupled in series between a positive DC rail and a negative DC rail. A first pole switch bank of the inverter may comprise a plurality of first pole switches. A first pole may be electrically coupled to the first pole switch bank. A control circuit may comprise at least one processor that is programmed to alternately switch the first pole switch bank to a first state of the first pole switch bank in which the first pole is electrically coupled to the positive DC rail, a second state of the first pole switch bank in which the first pole is electrically coupled between the first capacitor and the second capacitor, a third state of the first pole switch bank in which the first pole is electrically coupled between the second capacitor and the third capacitor, a fourth state of the first pole switch bank in which the first pole is electrically coupled to the negative DC rail.

PRIORITY

This application claims the benefit of U.S. Provisional Application Ser.No. 62/048,880 filed on Sep. 11, 2014, which is incorporated herein byreference in its entirety.

BACKGROUND

Many electric devices, such as motor, refrigerators, cars, fans, etc.are configured to utilize alternating current (AC). Although the powergrid provides AC, many other power supplies generate direct current(DC), including photovoltaic cells, fuel cells, batteries, etc. ToInverters are used to power AC devices with DC. Inverters receive DC andconvert it to AC that can be used, for example, to power an AC device.Conventional inverters, however, can be large and can generatesignificant heat.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a diagram showing one example of an inverter for convertingdirect current (DC) to alternating current (AC).

FIG. 2 is a diagram showing one example of an inverter system forconverting DC to AC.

FIG. 3 is a flowchart showing one example of a process flow that may beexecuted by the control circuit to generate a waveform utilizing theinverter of FIGS. 1 and 2.

FIG. 4 is a diagram showing one example of a waveform that may begenerated according to the process flow of FIG. 3.

FIG. 5 is a diagram showing time patterns for the switches of the firstpole switch bank during execution of the process flow of FIG. 3 tocreate the example waveform of FIG. 4.

FIG. 6 is a diagram showing one example of voltage and current afterfiltering of the waveform of FIG. 4.

FIG. 7 is a diagram showing one example of the charge on the capacitorsof the inverter of FIG. 1 during execution of the process flow of FIG.3.

FIG. 8 is a diagram showing one example of a housing for the invertersystem described herein.

FIGS. 9 and 10 show switching sequences (FIG. 9) and a resultingwaveform (FIG. 10) showing one example of an alternate switchingsequence that the control circuit may implement to control the switchesof the inverter.

FIG. 11 is a diagram showing another example of an inverter forconverting DC to AC.

FIG. 12 is a diagram showing yet another example of an inverter forconverting DC to AC.

FIGS. 13-14 show an alternate switching sequence that may be used inconjunction with the inverter of FIG. 1 to generate an output waveform.

FIG. 15 is a diagram showing an output waveform generated in accordancewith the switching sequence of FIGS. 13-14.

DETAILED DESCRIPTION

In the following description, reference is made to the accompanyingdrawings, which illustrate several examples of the present invention. Itis understood that other examples may be utilized and variousoperational changes may be made without departing from the spirit andscope of the present disclosure. The following detailed description isnot to be taken in a limiting sense, and the scope of the embodiments ofthe present invention is defined only by the claims of the issuedpatent.

Various examples are directed to a direct current (DC) to alternatingcurrent (AC) inverter comprising three capacitors, a first pole switchbank and a second pole switch bank. A DC input voltage may be providedto the inverter on a DC bus comprising a positive DC rail and a negativeDC rail. The output of the inverter may be provided between a first poleand a second pole, with the first pole electrically coupled to the firstswitch bank and the second pole electrically coupled to the secondswitch bank. The capacitors may be connected in series between thepositive DC rail and the negative DC rail. Accordingly, each of thethree capacitors may drop one-third (⅓) of the DC input voltage. Forexample, when the DC input voltage is a 450 Volt DC signal, eachcapacitor may drop 150 Volts. In some examples, the inverter may beconfigured to provide 2 kVA of power.

A control circuit may configure the first pole switch bank and thesecond pole switch bank to alternately connect the first and secondpoles to the series capacitors at different positions. For example, thecontrol circuit may configure the first pole switch bank to one of fourstates. In a first state, the first pole may be electrically coupled tothe positive DC rail, which may be at the DC input voltage. In a secondstate, the first pole may be electrically coupled between two of thecapacitors and the negative DC rail, drawing the first pole to a voltageof about two-thirds (⅔) of the DC input voltage. In a third state, thefirst pole may be electrically coupled between one of the capacitors andthe negative DC rail, drawing the first pole to a voltage of aboutone-third (⅓) of the DC input voltage. In a fourth state, the first polemay be electrically coupled to the negative DC rail, drawing the voltageof the first pole to zero.

The control circuit may similarly configure the second pole bank betweenone of four states to draw the second pole to the DC input voltage; ⅔ ofthe DC input voltage; ⅓ of the DC input voltage; and zero. The output ofthe inverter may be the difference between the voltage at the first poleand the voltage at the second pole. Accordingly, the inverter may haveseven possible output levels: DC input voltage; ⅔ DC input voltage; ⅓ DCinput voltage; zero; −⅓ DC input voltage; −⅔ DC input voltage and −DCinput voltage. The control circuit may be programmed, as describedherein, to cycle the first pole switch bank and the second pole switchbank according to a sequence that creates a suitable waveform (e.g., aPulse Width Modulated (PWM) waveform) between the poles, for example, asdescribed herein. A low-pass filter may be applied to the output of theinverter to generate an AC signal.

FIG. 1 is a diagram showing one example of an inverter 10 for convertingDC to AC. The inverter 10 may receive the DC input voltage at a DC buscomprising a positive DC rail 12 and a negative DC rail 14. For example,a voltage difference between the positive DC rail 12 and the negative DCrail 14 may be equal to the DC input voltage. The DC input voltage maybe any suitable value. In some examples, the DC input voltage may be 450Volts. In some examples, the DC input voltage may be 500 Volts. Anoutput of the inverter 10 may be taken between a first pole 8 and asecond pole 11. For example, the output of the inverter 10 may be avoltage difference between the first pole 8 and the second pole 11.

Three capacitors C1, C2, and C3 may be electrically coupled in seriesbetween the positive DC rail 12 and the negative DC rail 14. Thecapacitors C1, C2, C3 may be of any suitable type and have any suitablecapacitance. In some examples configured to generate a 240 V rms outputsignal, the capacitors C1, C2, C3 may be selected with a capacitance of1000 μF. A first terminal 20 of the capacitor C1 may be electricallycoupled to the positive DC rail 12. A second terminal 22 of thecapacitor C1 may be electrically coupled to a first terminal 24 of thecapacitor C2. A second terminal 26 of the capacitor C2 may beelectrically coupled to a first terminal 28 of the capacitor C3. Asecond terminal 30 of the capacitor C3 may be electrically coupled tothe negative DC rail 14. In some examples, each capacitor may drop ⅓ ofthe DC input voltage. Accordingly, relative to the negative DC rail 14,the first terminal 20 of the capacitor C1 may be at the DC inputvoltage. The first terminal 24 of the capacitor C2 may be at ⅔ of the DCinput voltage. The first terminal 28 of the capacitor C3 may be at ⅓ ofthe DC input voltage. Also, the second terminal 30 of the capacitor C3may be at zero volts relative to the negative DC rail.

A first pole switch bank 16 may comprise switches S1 a, S2 a, S3 a, S4a, S5 a, S6 a that may be configured by the control circuit (FIG. 2) toalternately connect the first pole 8 to the capacitors C1, C2, C3 and/orDC rails 12, 14 to alternately draw the first pole 8 to the DC inputvoltage, ⅔ of the DC input voltage, ⅓ of the DC input voltage and zero,as described herein. First Pole 8 may be coupled to the emitter 42 ofthe switch S3 a. In FIG. 1, the switches S1 a, S2 a, S3 a, S4 a, S5 a,S6 a are shown as NPN-type bipolar junction transistors, although anyother suitable type of transistor or other switch may be used. In someexamples, each switch S1 a, S2 a, S3 a, S4 a, S5 a, S6 a may comprise anInsulated Gate Bipolar Transistor (IGBT). In some examples, each switchS1 a, S2 a, S3 a, S4 a, S5 a, S6 a may comprise an IGBT rated for 300Volts and 20 Amps, for example, in a TO-247 or TO-220 package. Also, insome examples, the switches S1 a, S2 a, S3 a, S4 a, S5 a, S6 a mayinclude transistors of other types such as, for example, Silicon Carbon(SiC) transistors, Gallium Nitride (GaN) transistors, etc. In variousexamples, switches of other architectures may also be used, such asfield effect transistors (FETs), etc. In examples where different typesof switches are used, different terminology may also be used. Forexample, the terminals of a FET may be referred to as the source, thedrain and the gate as opposed to the collector, the emitter and thebase.

In the example of FIG. 1, the switches S1 a, S2 a, S3 a, S4 a, S5 a, S6a are electrically coupled in series between the positive DC rail 12 andthe negative DC rail 14. For example, a collector 32 of the switch S1 ais electrically coupled to the positive DC rail 12. An emitter 34 of theswitch S1 a is electrically coupled to a collector 36 of the switch S2a. An emitter 38 of the switch S2 a is electrically coupled to acollector 40 of the switch S3 a. An emitter 42 of the switch S3 a iselectrically coupled to a collector 44 of the switch S4 a. An emitter 46of the switch S4 a is electrically coupled to a collector 48 of theswitch S5 a. An emitter 50 of the switch S5 a is electrically coupled toa collector 52 of the switch S6 a. An emitter 54 of the switch S6 a iselectrically coupled to the negative DC rail 14. The switches S1 a, S2a, S3 a, S4 a, S5 a, S6 a are shown in the example of FIG. 1 to be NPNbipolar junction transistors. In examples where other types of switchesare used, however, (e.g., PNP bipolar junction transistors, Field EffectTransistors (FETs), etc.) different circuit topologies may be utilizedto generate the states of the first pole 8 described herein. Also, eachof the switches S1 a, S2 a, S3 a, S4 a, S5 a, S6 a may comprise a basethat may be electrically coupled to the control circuit (FIG. 2). Insome examples, the control circuit may draw the base of a switch S1 a,S2 a, S3 a, S4 a, S5 a, S6 a high to close the switch and low to openthe switch. In some examples, each switch S1 a, S2 a, S3 a, S4 a, S5 a,S6 a may comprise a bypass diode 80, 82, 84, 86, 88, 90 connectedopposite the polarity of the switch S1 a, S2 a, S3 a, S4 a, S5 a, S6 a.For example, when the switch S1 a is closed, it may conduct current fromits collector 32 to its emitter 34. Bypass diode 80 may be connectedbetween the collector 32 and emitter 34 to permit current to flow in theopposite direction. This may facilitate the provision of differentvoltages at the first pole 8 as described herein.

The first pole switch bank 16 may also comprise clamping diodes D1 a, D2a, D3 a, D4 a. The clamping diodes D1 a, D2 a, D3 a, D4 a may beconnected to limit the voltage drop across each of the individualswitches S1 a, S2 a, S3 a, S4 a, S5 a, S6 a. For example, the clampingdiodes D1 a, D2 a, D3 a, D4 a may be connected, as shown and describedherein, to ensure that no single switch S1 a, S2 a, S3 a, S4 a, S5 a, S6a drops more than ⅓ of the DC input voltage. In this way, the switchesS1 a, S2 a, S3 a, S4 a, S5 a, S6 a may utilize components with voltageratings based on a fraction of the DC input voltage (e.g., ⅓) instead ofthe entire DC input voltage. One example safety rating for inverterswitches is 100%. Accordingly, a switch that could drop a an example DCinput voltage of 450 Volts may be selected with a voltage rating of twotimes 450 Volts, or 900 Volts. In the example of FIG. 1, however, themaximum voltage drop across any individual switch S1 a, S2 a, S3 a, S4a, S5 a, S6 a may be ⅓ of 450 Volts, or 150 Volts. Accordingly, with a100% safety margin, the switches S1 a, S2 a, S3 a, S4 a, S5 a, S6 a maybe selected to support a maximum voltage drop of 300 Volts. Becauseswitches with lower voltage ratings are often smaller, this may reducethe size of the inverter 10.

TABLE 1 below shows example configurations of the switches S1 a, S2 a,S3 a, S4 a, S5 a, S6 a to bring about four states of the first poleswitch bank 16:

TABLE 1 State Switches Closed Voltage at Pole 8 First S1a, S2a, S3a DCinput voltage Second S2a, S3a, S4a ⅔ DC input voltage Third S3a, S4a,S5a ⅓ DC input voltage Fourth S4a, S5a, S6a Zero (negative DC rail)In the first state, switches S1 a, S2 a and S3 may be closed allowingcurrent to flow from the respective collectors 32, 36, 40 to therespective emitters 34, 38, 42. Switches S4 a, S5 a and S6 a may beopen, preventing current from flowing through those switches. In thisconfiguration, first pole 8 may be coupled to the positive DC rail 12via the closed switches S1 a, S2 a, S3 a. Accordingly, the voltage atthe first pole 8 relative to the negative DC rail may be equal to the DCinput voltage. In the first state, first pole 8 may source current fromthe capacitors C1, C2 and C3, which may flow through switches S1 a, S2a, S3 a to first pole 8. The first pole 8 may also sink current to thecapacitor C1 via diodes 80, 82, 84, or draw no current. Whether thefirst pole 8 sources current, sinks current, or draws no current maydepend on the load and state of the second switch bank and pole 11.

In the second state, switches S2 a, S3 a, S4 a may be closed whileswitches S1 a, S5 a and S6 a may be open. In this state, first pole 8may be coupled between the capacitor C1 and the capacitor C2 (e.g., atterminal 22 of capacitor C1 and/or terminal 24 of capacitor C2).Accordingly, the voltage at the first pole 8 relative to the negative DCrail may be equal to about ⅔ of the DC input voltage. In the secondstate, first pole 8 may source current from the capacitors C2 and C3 viaswitches S2 a and S3 a, may sink current to capacitor C2 via switch S4a, or draw no current, again depending on the load and the state of thesecond switch bank and second pole 11.

In the third state, switches S3 a, S4 a, S5 a may be closed whileswitches S1 a, S2 a and S6 a are open. In the third state, first pole 8may be coupled between the capacitor C2 and the capacitor C3 (e.g., atterminal 26 of the capacitor C2 and/or terminal 28 of the capacitor C3).Accordingly, the voltage at first pole 8 may be equal to about ⅓ of theDC input voltage. In the third state, first pole 8 may source currentfrom the capacitor C3 via the switch S3 a, may sink current to thecapacitor C3 via the switches S4 a and S5 a, or may draw no current,again depending on the load and the state of the second switch bank andsecond pole 11.

In the fourth state, switches S4 a, S5 a, S5 a may be closed whileswitches S1 a, S2 a and S3 a are open. In the fourth state, first pole 8may be coupled to the negative DC rail 14. Accordingly, the voltage atfirst pole 8 may be about zero relative to the positive DC rail 12. Inthe fourth state, first pole 8 may source current via the diodes 86, 88,90, may sink current to the negative DC rail 14 via switches S4 a, S4 a,S6 a, or may draw no current, again depending on the load and the stateof the second switch bank and second pole 11.

In various examples, the second pole switch bank 18 may be configuredsimilar to the first pole switch bank 16. For example, the switches S1b, S2 b, S3 b, S4 b, S5 b, S6 b may be or comprise components similar tothose described above with respect to the switches S1 a, S2 a, S3 a, S4a, S5 a, S6 a. The switches S1 b, S2 b, S3 b, S4 b, S5 b, S6 b may alsobe configured similar to the switches of the first pole switch bank 16to alternately connect the second pole 11 to the capacitors C1, C2, C3and/or DC rails 12, 14 to alternately draw the second pole 11 to the DCinput voltage, ⅔ of the DC input voltage, ⅓ of the DC input voltage andzero, as described herein. Second Pole 11 may be coupled to the emitter66 of the switch S3 b. The switches S1 b, S2 b, S3 b, S4 b, S5 b, S6 b,in the example shown in FIG. 1, are electrically coupled in seriesbetween the positive DC rail 12 and the negative DC rail 14. Forexample, a collector 56 of the switch S1 b is electrically coupled tothe positive DC rail 12. An emitter 58 of the switch S1 b iselectrically coupled to a collector 60 of the switch S2 a. An emitter 62of the switch S2 b is electrically coupled to a collector 64 of theswitch S3 a. An emitter 66 of the switch S3 b is electrically coupled toa collector 68 of the switch S4 a. An emitter 70 of the switch S4 b iselectrically coupled to a collector 72 of the switch S5 a. An emitter 74of the switch S5 b is electrically coupled to a collector 76 of theswitch S6 a. An emitter 78 of the switch S6 b is electrically coupled tothe negative DC rail 14. As described, the switches S1 b, S2 b, S3 b, S4b, S5 b, S6 b are shown in the example of FIG. 1 to be NPN bipolarjunction transistors. In examples where other types of switches are used(e.g., PNP bipolar junction transistors, FETs, etc.) different circuittopologies may be utilized to generate the states of the first pole 8described herein. Also, each of the switches S1 b, S2 b, S3 b, S4 b, S5b, S6 b may comprise a base that may be electrically coupled to thecontrol circuit (FIG. 2). In some examples, the control circuit may drawthe base of a switch S1 b, S2 b, S3 b, S4 b, S5 b, S6 b high to closethe switch and low to open the switch. In some examples, each switchSlb, S2 b, S3 b, S4 b, S5 b, S6 b may comprise a bypass diode 92, 94,96, 98, 99, 97 connected opposite the polarity of the switch S1 b, S2 b,S3 b, S4 b, S5 b, S6 a. For example, when the switch S1 b is closed, itmay conduct current from its collector 92 to its emitter 34. Bypassdiode 92 may be connected between the collector 32 and emitter 34 topermit current to flow in the opposite direction. This may facilitatethe provision of different voltages at the first pole 8 as describedherein.

The second pole switch bank 18 may also comprise clamping diodes D1 b,D2 b, D3 b, D4 b. The clamping diodes D1 b, D2 b, D3 b, D4 b may beconnected, similar to the clamping diodes D1 a, D2 a, D3 a, D4 a tolimit the voltage drop across each of the individual switches S1 b, S2b, S3 b, S4 b, S5 b, S6 a. For example, the clamping diodes D1 b, D2 b,D3 b, D4 b may be connected, as shown and described herein, to ensurethat no single switch S1 b, S2 b, S3 b, S4 b, S5 b, S6 b drops more than⅓ of the DC input voltage allowing the use of switches S1 b, S2 b, S3 b,S4 b, S5 b, S6 b with lower voltage ratings. As with the first poleswitch bank 16, the control circuit (FIG. 2) may be programmed toconfigure the second pole switch bank 18 to four states, as indicated byTABLE 2:

TABLE 2 State Switches Closed Voltage at First Pole 8 First S1b, S2b,S3b DC input voltage Second S2b, S3b, S4b ⅔ DC input voltage Third S3b,S4b, S5b ⅓ DC input voltage Fourth S4b, S5b, S6b Zero (negative DC rail)

The control circuit (FIG. 2) may be programmed to cycle the first poleswitch bank 16 and the second pole switch bank 18 between statesaccording to one or more switching sequences to generate differentoutput voltage levels for the inverter 10 (e.g. across the first andsecond poles 8, 11). Example switching sequences are described hereinwith respect to FIGS. 3-10. In some examples, the inverter 10 may beconfigured to assume seven different output voltages: (1) the DC inputvoltage; (2) ⅔ of the DC input voltage; (3) ⅓ of the DC input voltage;(4) zero; (5) −⅓ of the DC input voltage; (6) −⅔ of the DC inputvoltage; and (7) −1 of the DC input voltage. In some examples, thecontrol circuit may cycle the switch banks 16, 18 between states togenerate a waveform as the output of the inverter 10, for example, asdescribed herein.

TABLE 3 below shows states of the pole switch banks 16, 18 thatconfigure the inverter 10 to provide different output voltages:

TABLE 3 Output Level First Pole Switch Bank State(s) Second Pole SwitchBank State(s) DC input (1) First (First Pole 8 = DC input (1) Fourth(Second Pole 11 = Zero) voltage voltage) ⅔ DC input (1) First (FirstPole 8 = DC input (1) Third (Second Pole 11 = ⅓ DC voltage voltage)input voltage) (2) Second (First Pole 8 = ⅔ DC (2) Fourth (Second Pole11 = zero) input voltage) ⅓ DC input (1) First (First Pole 8 = DC input(1) Second (Second Pole 11 = ⅔ DC voltage voltage) input voltage) (2)Second (First Pole 8 = ⅔ DC (2) Third (Second Pole 11 = ⅓ DC inputvoltage) input voltage) (3) Third (First Pole 8 = ⅓ DC (3) Fourth(Second Pole 11 = zero) input voltage) 0 (negative (1) First (First Pole8 = DC input (1) First (Second Pole 11 = DC input rail of DC voltage)voltage) input (2) Second (First Pole 8 = ⅔ DC (2) Second (Second Pole11 = ⅔ DC voltage) input voltage) input voltage) (3) Third (First Pole 8= ⅓ DC (3) Third (Second Pole 11 = ⅓ DC input voltage) input voltage)(4) Fourth (First Pole 8 = zero) (4) Fourth (Second Pole 11 = zero) −⅓DC (1) Second (First Pole 8 = ⅔ DC (1) First (Second Pole 11 = DC inputinput voltage input voltage) voltage) (2) Third (First Pole 8 = ⅓ DC (2)Second (Second Pole 11 = ⅔ DC input voltage) input voltage) (3) Fourth(First Pole 8 = zero) (3) Third (Second Pole 11 = ⅓ DC input voltage) −⅔DC (1) Third (First Pole 8 = ⅓ DC (1) First (Second Pole 11 = DC inputinput voltage input voltage) voltage) (2) Fourth (First Pole 8 = zero)(2) Second (Second Pole 11 = ⅔ DC input voltage) −DC input (1) Fourth(First Pole 8 = zero) (1) First (Second Pole 11 = DC input voltagevoltage)

In various examples, the inverter 10 may provide the DC input voltageacross the poles 8, 11 when the first pole switch bank 16 is in thefirst state (see TABLE 1) and the second pole switch bank is in thefourth state (see TABLE 2). For example, when the first pole switch bank16 is in the first state, it may draw the first pole 8 to the DC inputvoltage. When the second pole switch bank 18 is in the fourth state, itmay draw the second pole 11 to zero (e.g., the negative DC railvoltage). Accordingly, the voltage between the poles 8, 11 may be aboutequal to the DC input voltage.

In various examples, the inverter 10 may provide ⅔ of the DC inputvoltage across the poles 8, 11 in two different configurations of theswitch banks 16, 18. For example, the inverter 10 may provide ⅔ of theDC input voltage across the poles 8, 11 when the first pole switch bank16 is in the first state and the second pole switch bank 18 is in thethird state. In the first state, the first pole switch bank 16 may drawthe first pole 8 to the DC input voltage. In the third state, the secondpole switch bank may draw the second poll 11 to ⅓ of the DC inputvoltage. Accordingly, the voltage between the poles 8, 11 may be aboutequal to the difference, e.g., ⅔ of the DC input voltage. In someexamples, the inverter 10 may also provide ⅔ of the DC input voltageacross the poles 8, 11 when the first pole switch bank 16 is in thesecond state and the second pole switch bank 18 is in the fourth state.In the second state, the first pole switch bank 16 may draw the firstpole 8 to about ⅔ of the DC input voltage. In the fourth state, thesecond pole switch bank may draw the second pole 11 to zero.Accordingly, the voltage between the poles 8, 11 may be equal to thedifference, e.g., ⅔ of the DC input voltage.

In various examples, there may be three combinations of switch bankstates that cause the inverter 10 to provide about ⅓ of the DC inputvoltage across the poles 8, 11. For example, when the first pole switchbank 16 is in the first state and the second pole switch bank 18 is inthe third state, the first pole 8 and second pole 11 may be drawn to theDC input voltage and ⅔ of the DC input voltage, respectively. Thedifference between the voltage at the poles 8, 11, then, may be ⅓ of theDC input voltage. Similarly, ⅓ of the DC input voltage may appear acrossthe poles 8, 11 when the first pole switch bank 16 is in the secondstate (e.g., ⅔ DC input voltage at pole 8) and the second pole switchbank 18 is in the third state (e.g., ⅓ DC input voltage at pole 11).Also, ⅓ of the DC input voltage may appear across the poles 8, 11 whenthe first pole switch bank 16 is in the third state (e.g., ⅓ of the DCinput voltage at pole 8) and the second pole switch bank 18 is in thefourth state (e.g., zero at pole 11).

In various examples, the output of the inverter 10 at the poles 8, 11may be equal to zero when the pole switch banks 16, 18 are in the samestate and, therefore, the poles 8, 11 at the same voltage. For example,the poles 8, 11 may be at the same voltage in four state combinations:when both banks 16, flare in the first state; when both banks 16, 18 arein the second state; when both banks 16, 18 are in the third state; andwhen both banks 16, 18 are in the fourth state.

In various examples, there may also be three combinations of switch bankstates that cause the inverter 10 to provide about −⅓ of the DC inputvoltage across the poles 8, 11. For example, when the first pole switchbank 16 is in the second state (e.g., ⅔ DC input at the pole 8) and thesecond pole switch bank 18 is in the first state (e.g., ⅓ DC input atthe pole 11), then the voltage difference across the poles 8, 11 may be−⅓ of the DC input voltage. The voltage difference across the poles 8,11 may also be −⅓ of the DC input voltage when the first pole switchbank 16 is in the third state (e.g., ⅓ DC input voltage at the pole 8)and the second pole switch bank 18 is in the second state (e.g., ⅔ DCinput voltage at the pole 11). Similarly, the voltage difference acrossthe poles 8, 11 may also be ⅓ of the DC input voltage when the firstpole switch bank 16 is in the fourth state (e.g., zero at the pole 8)and the second pole switch bank is in the third state (e.g., ⅓ DC inputvoltage at the pole 11).

In various examples, there may be two combinations of switch bank statesthat cause the inverter to provide about −⅔ of the DC input voltageacross the poles 8, 11. For example, the output of the inverter may beabout −⅔ of the DC input voltage when the first pole switch bank 16 isin the third state (e.g., ⅓ DC input voltage at the pole 8) and thesecond pole switch bank 18 is at the first state (e.g., DC input voltageat the pole 11). Also, for example, the output of the inverter may beabout −⅔ of the DC input voltage when the first pole switch bank 16 isin the fourth state (e.g., zero at the pole 8) and the second poleswitch bank 18 is in the second state (e.g., ⅔ DC input voltage at thepole 11). Additionally, there may be a single combination of switch bankstates that draw the output of the inverter 10 to the negative of the DCinput voltage such as, for example, when the first pole switch bank 16is in the fourth state (e.g., zero at the pole 8) and the second poleswitch bank 18 is at the first state (e.g., DC input voltage at the pole11).

FIG. 2 is a diagram showing one example of an inverter system 100comprising the example inverter 10. In addition to the inverter 10, theinverter system 100 comprises a DC source 102, a control circuit 114 anda filter 116. The DC source may be any suitable DC source including, forexample, a battery, a solar cell or set of solar cells, a fuel cell orset of fuel cells, etc. The DC source 102 may provide a DC input havingthe DC input voltage described herein. An example DC input 118 is shown.In some examples, the DC source 102 may provide a DC input voltage of450 Volts. The DC input may be provided to the inverter 101 via a DC bus104 comprising the positive DC rail 12 and a negative DC rail 14. Acontrol circuit 114 may configure the various switches of the inverter10 to set its output voltage. In some examples, the control circuit 114may configure the switches according to a sequence to generate awaveform 120 between the poles 8, 11. The control circuit 114 maycomprise any suitable hardware for configuring the switches of theinverter 10. In some examples, the control circuit 114 may comprise oneor more microprocessors, microcontrollers or other suitable processorsalong with associated memory. In addition to or instead of a processor,the control circuit 114 may comprise other control hardware such as, forexample, a hardwired state machine implemented utilizing logic gates. Astate machine may be implemented, for example, utilizing an applicationspecific integrated circuit (ASIC) or other suitable hardware. In someexamples, the control circuit 114 may comprise an output stage (notshown) for translating a digital output of a microprocessor to an analogcurrent that may be provided to the bases of the switches of theinverter 10 to close the switches.

The waveform 120 may be provided to a low-pass filter 116, which mayprovide an output AC signal 122. The low-pass filter 116 may comprisevarious circuit components including, for example, capacitors,inductors, etc. The low-pass filter 116 may remove high frequencycomponents of the waveform 120 including, for example, the switchingfrequency and its related harmonics. As described herein, the switchingfrequency, in some examples, may be about 10 kHz. Some examples of thelow-pass filter 116 may be and/or comprise an LC circuit. In one examplewhere the DC input voltage is 450 Volts and the output is a 240 Volt RMSsine wave, the inductor may have an inductance of about 75 μH and thecapacitor may have a capacitance of 80 μF. In this example, the ACsignal 122 may be sinusoidal with a total harmonic distortion (THD) of<5%. Also, in some examples, the low-pass filter 116 may be implementeddigitally utilizing a digital signal processor (DSP) or other suitableprocessor.

In various examples, the AC signal 122 may be configured to meetstandards for an electric grid network, either to provide the output ofthe system 100 to an electric grid or to power devices configured tooperate on the electric grid. For example, the AC signal 122 may be a 60Hz sine wave with a 120 Volts RMS. In other examples, the AC signal maybe a 60 Hz sine wave at 240 Volts RMS. In various examples, because theinverter 10 has seven available levels, the control circuit 114 maymodulate the various switches to create a waveform 120 with fewer DC orlower frequency content. As a result, the capacitance and/or inductanceof active components of the filter 116 may be reduced, further reducingthe size of the system 100.

The control circuit 114 may modulate the various switches according toone or more sequences to generate the waveform 120. FIG. 3 is aflowchart showing one example of a process flow 200 that may be executedby the control circuit 114 to generate a waveform 120. At 202, thecontrol circuit 114 may cycle the pole switch banks 16, 18 sequentiallyback-and-forth between a sequence of states that draw the output of theinverter 10 alternately to zero and ⅓ of the DC input voltage. Forexample, TABLE 4 below illustrates a sequence of switch bank states thatcycle the switch banks 16, 18 to draw the output of the inverter 10between zero and ⅓ of the DC input voltage:

TABLE 4 Second Bank 18 Output Voltage First Bank 16 State State (FirstPole 8 - (Switches Closed) (Switches Closed) Second Pole 11) 1 FirstFirst 0 Volts (S1a, S2a, S3a) (S1b, S2b, S3b) (DC input voltage - DCinput voltage) 2 First Second ⅓ DC input voltage (S1a, S2a, S3a) (S2b,S3b, S4b) (DC input voltage - ⅔ DC input voltage) 3 Second Second 0Volts (S2a, S3a, S4a) (S2b, S3b, S4b) (⅔ DC input voltage - ⅔ DC inputvoltage) 4 Second Third ⅓ DC input voltage (S2a, S3a, S4a) (S3b, S4b,S5b) (⅔ DC input voltage - ⅓ DC input voltage) 5 Third Third 0 Volts(S3a, S4a, S5a) (S3b, S4b, S5b) (⅓ DC input voltage - ⅓ DC inputvoltage) 6 Third Fourth ⅓ DC input voltage (S3a, S4a, S5a) (S4b, S5b,S6b) (⅓ DC input voltage - zero) 7 Fourth Fourth 0 Volts (S4a, S5a, S6a)(S4b, S5b, S6b) (zero-zero)The control circuit 114 may configure the pole switch banks 16, 18 totraverse the sequence of states shown in TABLE 4 sequentiallyback-and-forth. For example, the control circuit 114 may proceed fromthe states of Row 1 (First, First) to the states of Row 2 (First,Second), to the states of Row 3 (Second, Second), to the states of Row 4(Second, Third), to the states of Row 5 (Third, Third), to the states ofRow 6 (Third, Fourth), to the states of Row 7 (Fourth, Fourth) and backagain. For example, when the control circuit 114 has configured the poleswitch banks 16, 18 to the states of Row 7 (Fourth, Fourth), it may nextproceed to the states of Row 6 (Third, Fourth), to the states of Row 5(Third, Third) and so on. When the control circuit 114 again configuresthe pole switch banks 16, 18 in the states of Row 1 (First, First) itmay proceed again to the set of state sin Row 2 and so on. In someexamples, each of the transitions shown in TABLE 4 and executed at 202may involve a change in state of just two of the 12 switches of theinverter 10. For example, between the states of Row 1 and the states ofRow 1, switch S1 b is opened and switch S4 b is closed. Similarly,between the states of Row 2 and the states of Row 3 switch S1 a isopenedand switch S3 a is closed. This configuration may minimize switchinglosses in the inverter 10, which may increase its efficiency.

The control circuit 114 may continue to cycle sequentiallyback-and-forth between states providing zero and ⅓ of the DC inputvoltage at the output of the inverter for a first period. The firstperiod may be of any suitable length and may, for example, be somefraction of the total period of the desired AC output 122. The length ofthe first period may also be selected to affect the shape of the ACoutput 122. For example, when the output frequency is 60 Hz and theoutput wave shape is a sine wave, the first period may be about 1 ms.FIG. 4 is a diagram showing one example of a waveform 300 that may begenerated according to the process flow 200. In the example shown inFIG. 4, the DC input voltage is 450 Volts. Accordingly, during the firstperiod 302, the control circuit 114 cycles the output between zero and150 Volts. Also, in the example of FIG. 4, the first period 302 extendsfrom zero to 1 ms.

Referring back to FIG. 3, at 204, the control circuit 114 may cycle thepole switch banks 16, 18 sequentially back-and-forth between states thatdraw the output of the inverter alternately to ⅓ of the DC input voltageand ⅔ of the DC input voltage. For example, TABLE 5 below illustrates asequence of switch bank states that cycle the switch banks 16, 18 todraw the output of the inverter 10 between ⅓ of the DC input voltage and⅔ of the DC input voltage:

TABLE 5 Second Bank 18 Output Voltage First Bank 16 State State (FirstPole 8 - (Switches Closed) (Switches Closed) Second Pole 11) 1 FirstSecond ⅓ DC input voltage (S1a, S2a, S3a) (S2b, S3b, S4b) (DC inputvoltage - ⅔ DC input voltage) 2 First Third ⅔ DC input voltage (S1a,S2a, S3a) (S3b, S4b, S5b) (DC input voltage - ⅓ DC input voltage) 3Second Third ⅓ DC input voltage (S2a, S3a, S4a) (S3b, S4b, S5b) (⅔ DCinput voltage - ⅓ DC input voltage) 4 Second Fourth ⅔ DC input voltage(S2a, S3a, S4a) (S4b, S5b, S6b) (⅔ DC input voltage - zero) 5 ThirdFourth ⅓ DC input voltage (S3a, S4a, S5a) (S4b, S5b, S6b) (⅓ DC inputvoltage - zero)The control circuit 114 may configure the pole switch banks 16, 18 totraverse the states shown in TABLE 5 sequentially back-and-forth. Forexample, the control circuit 114 may proceed from the states of Row 1(First, Second), to the states of Row 2 (First, Third), to the states ofRow 3 (Second, Third), to the states of Row 4 (Second, Fourth), to thestates of Row 5 (Third, Fourth) and then back to Row 4, Row 3, Row 2 andRow 1 again, as described above. The control circuit 114 may continue tocycle sequentially back-and-forth between the states shown in TABLE 5for a second period. In some examples, the second period may be 1 ms.For example, referring to FIG. 4, in the example second period 304, theoutput of the inverter 10 cycles between 150 Volts (⅓ of the 450 Volt DCinput voltage) and 300 Volts (⅔ of the 450 Volt DC input voltage).Similar to what was described at 202, the difference between eachconsecutive set of states in the sequence shown in TABLE 5 is theposition of two switches. Accordingly, to transition from one set ofstates to the next, the control circuit 114 may need to open a singleswitch and close a single switch.

Referring back to FIG. 3, at 206, the control circuit 114 may cycle thepole switch banks 16, 18 sequentially back-and-forth between states thatdraw the output of the inverter 10 between the DC input voltage and ⅔ ofthe DC input voltage. For example, TABLE 6 below illustrates a sequenceof switch bank states that cycle the switch banks 16, 18 to draw theoutput of the inverter 10 alternately to the DC input voltage and ⅔ ofthe DC input voltage:

TABLE 6 Second Bank 18 Output Voltage First Bank 16 State State (FirstPole 8 - (Switches Closed) (Switches Closed) Second Pole 11) 1 FirstThird ⅔ DC input voltage (S1a, S2a, S3a) (S3b, S4b, S5b) (DC inputvoltage - ⅓ DC input voltage) 2 First Fourth DC input voltage (S1a, S2a,S3a) (S4b, S5b, S6b) (DC input voltage - zero) 3 Second Fourth ⅔ DCinput voltage (S2a, S3a, S4a) (S4b, S5b, S6b) (⅔ DC input voltage -zero)The control circuit 114 may configure the pole switch banks 16, 18 totraverse the states shown in TABLE 6 sequentially back-and-forth. Forexample, the control circuit 114 may proceed from the states of Row 1(First, Third), to the states of Row 2 (First, Fourth), to the states ofRow 3 (Second, Fourth), to the states of Row 2 (First, Fourth) and soon. As shown, the difference between consecutive sets of states is theposition of two switches, allowing the control circuit 114 to movebetween any two consecutive set of states from the TABLE 6 by opening asingle switch and closing a single switch. The control circuit 114 maycontinue to cycle sequentially back-and-forth between the states shownin TABLE 6 for a third period. The third period, for example, may beabout 4 ms. Referring to FIG. 4, in the example third period 306, theoutput of the inverter 10 cycles between 300 Volts (⅔ of the 450 Volt DCinput voltage) and 450 Volts (the DC input voltage).

Again referring back to FIG. 3, as 208, the control circuit 114 mayagain cycle the pole switch banks 16, 18 sequentially back-and-forthbetween states that draw the output of the inverter 10 between ⅓ of theDC input voltage and ⅔ of the DC input voltages, for example, asdescribed herein above with respect to TABLE 5. This may continue for afourth period, which may be, for example, lms. This is illustrated in inFIG. 4 by the example fourth period 308. At 210 of FIG. 3, the controlcircuit 114 may cycle the pole switch banks 16, 18 sequentiallyback-and-forth between states that draw the output of the inverter 10 to⅓ of the DC input voltage and zero, for example, as described hereinabove with respect to TABLE 4. This may continue for a fifth period,which may be, for example, 1 ms. An example fifth period 310 is shown inFIG. 4.

At 212 of the process flow 200, the control circuit 114 may cycle thepole switch banks 16, 18 sequentially back-and-forth between states thatdraw the output of the inverter 10 between to zero and −⅓ of the DCinput voltage. For example, TABLE 7 below illustrates a sequence ofswitch bank states that cycle the switch banks 16, 18 to draw the outputof the inverter 10 alternately to zero and −⅓ of the DC input voltage:

TABLE 7 Second Bank 18 Output Voltage First Bank 16 State State (FirstPole 8 - (Switches Closed) (Switches Closed) Second Pole 11) 1 FirstFirst 0 Volts (S1a, S2a, S3a) (S1b, S2b, S3b) (DC input voltage - DCinput voltage) 2 Second First −⅓ DC input voltage (S2a, S3a, S4a) (S1b,S2b, S3b) (⅔ DC input voltage - ⅓ DC input voltage) 3 Second Second 0Volts (S2a, S3a, S4a) (S2b, S3b, S4b) (⅔ DC input voltage - ⅔ DC inputvoltage) 4 Third Second −⅓ DC input voltage (S3a, S4a, S5a) (S2b, S3b,S4b) (⅓ DC input voltage - ⅔ DC input voltage) 5 Third Third 0 Volts(S3a, S4a, S5a) (S3b, S4b, S5b) (⅓ DC input voltage - ⅓ DC inputvoltage) 6 Fourth Third −⅓ DC input voltage (S4a, S5a, S6a) (S3b, S4b,S5b) (zero - ⅓ DC input voltage) 7 Fourth Fourth 0 Volts (S4a, S5a, S6a)(S4b, S5b, S6b) (zero-zero)The control circuit 114 may configure the pole switch banks 16, 18 totraverse the states shown in TABLE 7 sequentially back-and-forth. Forexample, the control circuit 114 may proceed from the states of Row 1(First, First), to the states of Row 2 (Second, First), to the states ofRow 3 (Second, Second), to the states of Row 4 (Third, Second), to thestates of Row 5 (Third, Third), to the states of Row 6 (Fourth, Third),to the states of Row 7 (Fourth, Fourth), and then back to Rows 6, 5, 4,3, 2 and 1 again, and so on, as described above. The control circuit 114may continue to cycle sequentially back-and-forth between the statesshown in TABLE 7 for a sixth period, which may be about 1 ms, asdescribed above. Similar to the sequences shown at TABLES 4, 5 and 6,each consecutive set of states from the TABLE 7 may differ only by thepositions of two switches. Also, FIG. 4 shows an example sixth period312. In the example of FIG. 4, during the sixth period 312, the outputof the inverter cycles between zero and −150 Volts (−⅓ of the DC inputvoltage).

At 214 of the process flow 200, the control circuit may cycle the poleswitch banks 16, 18 sequentially back-and-forth between states that drawthe output of the inverter 10 between −⅓ of the DC input voltage and −⅔of the DC input voltage. For example, TABLE 8 below illustrates asequence of switch bank states that cycle the switch banks 16, 18 todraw the output of the inverter 10 alternately between −⅓ of the DCinput voltage and −⅔ of the DC input voltage:

TABLE 8 Second Bank 18 Output Voltage First Bank 16 State State (FirstPole 8 - (Switches Closed) (Switches Closed) Second Pole 11) 1 SecondFirst −⅓ DC input voltage (S2a, S3a, S4a) (S1b, S2b, S3b) (⅔ DC inputvoltage - DC input voltage) 2 Third First −⅔ DC input voltage (S3a, S4a,S5a) (S1b, S2b, S3b) (⅓ DC input voltage - DC input voltage) 3 ThirdSecond −⅓ DC input voltage (S3a, S4a, S5a) (S2b, S3b, S4b) (⅓ DC inputvoltage - ⅔ DC input voltage) 4 Fourth Second −⅔ DC input voltage (S4a,S5a, S6a) (S2b, S3b, S4b) (zero - ⅔ DC input voltage) 5 Fourth Third −⅓DC input voltage (S4a, S5a, S6a) (S3b, S4b, S5b) (zero - ⅓ DC inputvoltage)The control circuit 114 may configure the pole switch banks 16, 18 totraverse the states shown in TABLE 8 sequentially back-and-forth. Forexample, the control circuit may proceed from the states of Row 1(Second, First), to the states of Row 2 (Third, First), to the states ofRow 3 (Third, Second), to the states of Row 4 (Fourth, Second), to thestates of Row 5 (Fourth, Third) and then back to Row 4, Row 3, Row 2 andRow 1 again, as described above. The control circuit 114 may continue tocycle sequentially back-and-forth between the states shown in TABLE 8for a seventh period. In some examples, the seventh period may be 1 ms.For example, referring to FIG. 4, in the example seventh period 314, theoutput of the inverter 10 cycles between −150 Volts (⅓ of the 450 VoltDC input voltage) and −300 Volts (−⅔ of the 450 Volt DC input voltage).Similar to what was described at 202, it is noted that the differencebetween each consecutive set of states is the position of two switches.

At 216 of the process flow 200, the control circuit 114 may cycle thepole switch banks 16, 18 sequentially back-and-forth between states thatdraw the output of the inverter 10 alternately to the negative DC inputvoltage and −⅔ of the DC input voltage. For example, TABLE 9 belowillustrates a sequence of switch bank states that cycle the switch banks16, 18 to draw the output of the inverter 10 alternately to the negativeDC input voltage and −⅔ of the DC input voltage:

TABLE 9 Second Bank 18 Output Voltage First Bank 16 State State (FirstPole 8 - (Switches Closed) (Switches Closed) Second Pole 11) 1 ThirdFirst −⅔ DC input voltage (S3a, S4a, S5a) (S1b, S2b, S3b) (⅓ DC inputvoltage - DC input voltage) 2 Fourth First −DC input voltage (S4a, S5a,S6a) (S1b, S2b, S3b) (zero - DC input voltage) 3 Fourth Second −⅔ DCinput voltage (S4a, S5a, S6a) (S2b, S3b, S4b) (zero - ⅔ DC inputvoltage)The control circuit 114 may configure the pole switch banks 18 totraverse the state sets shown in TABLE 9 sequentially back-and-forth.For example, the control circuit 114 may proceed from the states of Row1 (Third, First), to the states of Row 2 (Fourth, First), to the satesof Row 3 (Second, Fourth) t the states of Row 2 (Fourth, First) and soon. As shown, the difference between consecutive sets of state is theposition of two switches, as described herein. The control circuit 114may continue to cycle sequentially back-and forth-between the statesshown in TABLE 9 for an eighth period The eighth period maybe, forexample, about 4 ms. Referring to FIG. 4, in the example eighth period316, the output of the inverter 10 cycles between −300 Volts (−⅔ of the450 Volt DC input voltage) and −450 Volts (the negative of the DC inputvoltage).

At 218, the control circuit 114 may again cycle the pole switch banks16, 18 sequentially back-and-forth between sets of states thatalternately draw the output of the inverter 10 to −⅓ of the DC inputvoltage and −⅔ of the DC input voltage, for example, as described hereinwith respect to TABLE 8. This may continue for a ninth period, which maybe, for example, 1 ms. An example ninth period 318 is shown in FIG. 4.At 220, the control circuit 114 may cycle the pole switch banks 16, 18sequentially back-and-forth between states that draw the output of theinverter 10 to zero and −⅓ of the DC input voltage, for example, asdescribed herein with respect to TABLE 7. This may continue for a tenthperiod, which may be, for example, 1 ms. An example tenth period 320 isshown in FIG. 4.

The process flow 200 may represent one period of a waveform such as 300,120. In various examples, the control circuit 114 may execute theprocess flow 200 repeatedly to generate a repeating waveform. Althoughexample lengths for the first through tenth periods are provided herein,it will be appreciated that the lengths of the periods may be modifiedto modify the shape of the resulting waveform. The frequency with whichthe control circuit cycles between consecutive sets of pole switch bankstates within each period (e.g., a switching frequency) may be anysuitable value. For example, higher switching frequencies may reduce thepresence of low frequency components in the waveform, thereby reducingthe inductance and capacitance needed in the filter 116. Also, forexample, higher switching frequencies may lead to more switching losses.In some examples, the switching frequency may be about 10 kHz.

FIG. 5 is a diagram 400 showing timing sequence for the switches S1 a,S2 a, S3 a, S4 a, S5 a, S6 a of the first pole switch bank 16 that maycause the inverter 10 to generate an output waveform similar to thewaveform 300. For example, the timing FIG. 6 is a diagram showing oneexample of voltage 502 and current 504 after filtering of the waveform300. For example, the voltage 502 may be 240 AC rms.

FIG. 7 is a diagram showing one example of the charge on the capacitorsC1, C2 and C3 during execution of the process flow 200. For example, asthe control circuit 114 cycles the pole switch banks 16, 18 through thestates indicated in TABLES 4-9, it may evenly draw and/or sink currentto each of the capacitors C1, C2, C3, resulting in smooth charge levelsfor the capacitors C1, C2, C3. For example, in each of the sequences ofswitch bank states in TABLES 4-9, the control circuit 114 steps theswitch banks from the first through fourth states and then back again.For example, referring to TABLE 4, in Row 1, no current is drawn orsunk. In Row 2, the first pole 8 draws from capacitors C1, C2 and C3while the second pole 11 draws and/or sinks from capacitors C2 and C3.In Row 3, both poles 8, 11 draws and/or sinks from capacitors C2 and C3.In Row 4, the first pole 8 draws and/or sinks from the second and thirdcapacitors C2, C3 while the second pole 11 draws and/or sinks from thethird capacitor C3. In Row 5, both poles draw and/or sink from capacitorC3 while in Row 7, no current is drawn. Accordingly, as the controlcircuit 114 cycles through the sets of states in TABLES 4-9, it alsosequentially draws current from and sinks current to the capacitors C1,C2, C3.

FIG. 8 is a diagram showing one example of a housing 600 for theinverter system 100. For example, an enclosure base PC board 602 mayhouse the switches S1 a, S2 a, S3 a, S4 a, S5 a, S6 a, S1 b, S2 b, S3 b,S4 b, S5 b, S6 b. For example, in FIG. 8, the twelve switches areillustrated as twelve TO-247 packages, each including two Insulated GateBipolar Junction Transistors (IGBJTs). The capacitors C1, C2, C3 arealso placed on the PC board 602, shown as DC link Capacitors. The filter116 is positioned on the PC board 602 and labeled L-C Filter. Anauxiliary power supply is also shown on the PC board 602. For example,the auxiliary power supply may provide a stepped-down DC power rail forone or more microprocessors of the controller 114. A second PC board 604may be positioned opposite the base PC board 602. The PC board 604 mayinclude the controller, embodied as a microcontroller and associatedhardware. The second PC board 604 may also comprise gate drives. Thegate drives, for example, may translate the digital output of themicrocontroller or microprocessor of the controller to a current orother suitable signal that may be provided to the bases or othersuitable terminal of the switches to close the switches. A fan, asillustrated, may be positioned between the PC boards 602, 604. Thevarious components shown in FIG. 8 may be positioned between enclosureportions 606, 608, as shown. In some examples, the housing 600 may beless than 40 square inches. This may allow the system 100 to have apower to volume ratio of between 50 W/in³ and 100 W/in³.

FIGS. 9 and 10 show switching sequences 702, 704 (FIG. 9) and aresulting waveform 706 showing one example of an alternate switchingsequence that the control circuit 114 may implement to control theswitches of the inverter 10. Switching sequence 702 shows states of thefirst pole switch bank 16. Switching sequence 704 shows states of thesecond pole switch bank 18. In the example of FIGS. 9 and 10, the DCinput voltage may be 500 Volts. The waveform 706 may follow a generallysinusoidal shape in increments of 166 Volts (e.g., 500 V/3). Forexample, seven levels of the waveform 706 may include 0 Volts, 166Volts, 333 Volts, 500 Volts, −166 Volts and −333 Volts.

In some examples, the output of the inverter 10 may be 0 Volts when boththe first and second pole switch banks 16, 18 are in the first state. Attransition 710, the control circuit 114 may cycle the second pole switchbank 18 to the second state, causing the output of the inverter 10 toincrease from 0 Volts to 166 Volts (e.g., ⅓ DC input voltage in theexample of FIGS. 9 and 10). At transition 712, the control circuit 114may cycle the second pole switch bank 18 to the third state, causing theoutput of the inverter 10 to increase from 166 Volts to 333 Volts (e.g.,⅔ of the DC input voltage in the example of FIGS. 9 and 10). Attransition 714, the control circuit 114 may cycle the second pole switchbank 18 to the fourth state, causing the output of the inverter 10 toincrease from 333 Volts to 500 Volts. At transition 716, the controlcircuit 114 may cycle the second pole switch bank 18 back to the thirdstate, causing the output of the inverter 10 to decrease from 500 Voltsto 333 Volts. At transition 718, the control circuit 114 may cycle thesecond pole switch bank 18 back to the second state, causing the outputof the inverter 10 to decrease from 333 Volts to 166 Volts. Attransition 720, the control circuit 114 may cycle the second pole switchbank 18 back to the first state, causing the output of the inverter 10to decrease to zero. At transition 722, the control circuit 114 maycycle the first pole switch bank 16 to the second state, causing theoutput of the inverter 10 to decrease from zero to −166 Volts. Attransition 724, the control circuit 114 may cycle the first pole switchbank 16 to the third state, causing the output of the inverter 10 todecrease from −166 Volts to −333 Volts. At transition 726, the controlcircuit 114 may cycle the first pole switch bank 16 to the fourth state,causing the output of the inverter 10 to decrease from −333 Volts to−500 Volts. At transition 728, the control circuit 114 may cycle thefirst pole switch bank 16 to the third state, causing the output of theinverter 10 to increase from −500 Volts to −333 Volts. At transition730, the control circuit 114 may cycle the first pole switch bank 16 tothe second state, causing the output of the inverter 10 to increase from−333 Volts to −166 Volts. At transition 732, the control circuit 114 maycycle the first pole switch bank 16 to the first state causing theoutput of the inverter to increase from −166 volts to zero. Relative tothe first transition at 710, this may complete one cycle of the waveform706.

FIGS. 9 and 10 also show a second cycle of the waveform 706. Forexample, At transition 734, the control circuit 114 may cycle the secondpole switch bank 18 to the second state, causing the output of theinverter 10 to increase from 0 Volts to 166 Volts (e.g., ⅓ DC inputvoltage in the example of FIGS. 9 and 10). At transition 736, thecontrol circuit 114 may cycle the second pole switch bank 18 to thethird state, causing the output of the inverter 10 to increase from 166Volts to 333 Volts (e.g., ⅔ of the DC input voltage in the example ofFIGS. 9 and 10). At transition 738, the control circuit 114 may cyclethe second pole switch bank 18 to the fourth state, causing the outputof the inverter 10 to increase from 333 Volts to 500 Volts. Attransition 740, the control circuit 114 may cycle the second pole switchbank 18 back to the third state, causing the output of the inverter 10to decrease from 500 Volts to 333 Volts. At transition 742, the controlcircuit 114 may cycle the second pole switch bank 18 back to the secondstate, causing the output of the inverter 10 to decrease from 333 Voltsto 166 Volts. At transition 744, the control circuit 114 may cycle thesecond pole switch bank 18 back to the first state, causing the outputof the inverter 10 to decrease to zero. At transition 746, the controlcircuit 114 may cycle the first pole switch bank 16 to the second state,causing the output of the inverter 10 to decrease from zero to −166Volts. At transition 748, the control circuit 114 may cycle the firstpole switch bank 16 to the third state, causing the output of theinverter 10 to decrease from −166 Volts to −333 Volts. At transition750, the control circuit 114 may cycle the first pole switch bank 16 tothe fourth state, causing the output of the inverter 10 to decrease from−333 Volts to −500 Volts. At transition 752, the control circuit 114 maycycle the first pole switch bank 16 to the third state, causing theoutput of the inverter 10 to increase from −500 Volts to −333 Volts. Attransition 754, the control circuit 114 may cycle the first pole switchbank 16 to the second state, causing the output of the inverter 10 toincrease from −333 Volts to −166 Volts. At transition 756, the controlcircuit 114 may cycle the first pole switch bank 16 to the first statecausing the output of the inverter to increase from −166 volts to zero.Relative to the first transition at 710, this may complete a secondcycle of the waveform 706. It will be appreciated that the transitionsbetween pole switch bank states shown in FIG. 9 are not the onlytransitions that would generate the waveform shown in FIG. 10.

In various examples, the inverter system 100 may generate an output ACsignal 122 with oscillating real power. Oscillations to the power of theoutput AC signal 122 may reflect onto the input side (e.g., the input DCsignal and its voltage), which may cause a harmonic ripple in the input.This harmonic ripple may be addressed in any suitable manner. Forexample, the capacitance of the capacitors C1, C2, C3 may be increasedto damp the ripple. Also, for example, an LC power filter may beutilized at the input (e.g., between the DC source 102 and the inverter10). In some examples, however, the control circuit 114 may beprogrammed to address input ripple by generating an inverse of theexpected input ripple on the AC signal 122. For example, the controlcircuit 114 may modify the switching frequency and/or the variousperiods of it switching sequence (e.g., such as the sequences describedherein) to generate a second harmonic of the expected ripple.

FIG. 11 is a diagram showing another example of an inverter 800 forconverting DC to AC. The inverter 800 may receive the DC input voltageat a DC bus comprising a positive DC rail 812 and a negative DC rail814. The inverter 800 may be incorporated into an inverter systemsimilar to the system 100 described herein with respect to FIG. 2. Forexample, switch banks 816, 818 of the inverter 800 may be controlled bya control circuit similar to the control circuit 114 described herein.Also, an output waveform of the inverter 800 may be provided to afilter, similar to the filter 116 described herein. The inverter 802comprises two capacitors C1′ and C2′. Similar to the inverter 10, eachof the capacitors C1′ and C2′ may drop ½ of the DC input voltage. Afirst switch bank 816 comprises four switches S1 a′, S2 a′, S3 a′ and S4a′. A first pole 808 is connected between the switches S1 a′, S2 a′, S3a′ and S4 a′ as illustrated. The switches S1 a′, S2 a′, S3 a′ and S4 a′may be configurable to three different states, as indicated by TABLE 10below:

TABLE 10 State Switches Closed Voltage at First Pole 808 First S1a′,S2a′ DC input voltage Second S2a′, S3a′ ½ DC input voltage Third S3a′,S4a′ Zero (negative DC rail)A second switch bank 818 also comprises four switches S1 b′, S2 b′, S3b′ and S4 b′ configurable to three different states, indicated by TABLE11 below:

TABLE 11 State Switches Closed Voltage at Second Pole 811 First S1b′,S2b′ DC input voltage Second S2b′, S3b′ ½ DC input voltage Third S3b′,S4b′ Zero (negative DC rail)Accordingly, the inverter 800 may be configurable to five differentlevels indicated by TABLE 12:

TABLE 12 Output Level First Pole Switch Bank State(s) Second Pole SwitchBank State(s) DC input (1) First (First Pole 808 = DC input (1) Third(Second Pole 811 = Zero) voltage voltage) ½ DC input (1) First (FirstPole 808 = DC input (1) Second (Second Pole 811 = ½ DC voltage voltage)input voltage) (2) Second (First Pole 808 = ½ DC (2) Third (Second Pole811 = Zero) input voltage) 0 (negative (1) First (First Pole 808 = DCinput (1) First (Second Pole 811 = DC input rail of DC voltage) voltage)input (2) Second (First Pole 808 = ½ DC (2) Second (Second Pole 811 = ½DC voltage) input voltage) input voltage) (3) Third (First Pole 808 =Zero) (3) Third (Second Pole 811 = Zero) −½ DC (1) Second (First Pole808 = ½ DC (1) First (Second Pole 811 = DC input input voltage inputvoltage) voltage) (2) Third (First Pole 808 = Zero) (2) Second (SecondPole 811 = ½ DC input voltage) −DC input (1) Third (First Pole 808 =Zero) (1) First (Second Pole 811 = DC input voltage voltage)

Any suitable switching sequence may be utilized for the inverter 800.For example, during a first period, the control circuit may modulate theswitch banks 816, 818 to toggle the output of the inverter 800 betweenthe zero and ½ of the DC input voltage. An example switching sequencefor doing so is provided by TABLE 13 below:

TABLE 13 First Bank Second Bank 816 State 818 State (Switches (SwitchesOutput Voltage Closed) Closed) (First Pole 808-Second Pole 811) 1 FirstFirst 0 Volts (S1a′, S2a′) (S1b′, S2b′) (DC input voltage-DC inputvoltage) 2 First Second ½ DC input voltage (S1a′, S2a′) (S2b′, S3b′) (DCinput voltage-½ DC input voltage) 3 Second Second 0 Volts (S2a′, S3a′)(S2b′, S3b′) (½ DC input voltage-½ DC input voltage) 4 Second Third ½ DCinput voltage (S2a′, S3a′) (S3b′, S4b′) (½ DC input voltage-Zero) 5Third Third 0 Volts (S3a′, S4a′) (S3b′, S4b′) (Zero-Zero)As described herein with respect to the switching of the inverter 10,the control circuit may configure the inverter 800 to traverse thesequence of states shown in TABLE 13 sequentially back-and-forth.

During a second period, the control circuit may modulate the switchbanks 816, 818 to toggle the output voltage of the inverter 800 between½ of the DC input voltage and the DC input voltage. An example switchingsequence for doing so is provided by TABLE 14 below:

TABLE 14 First Bank 816 State Second Bank 818 (Switches State OutputVoltage Closed) (Switches Closed) (First Pole 808-Second Pole 811) 1First Second ½ DC input voltage (S1a′, S2a′) (S2b′, S3b′) (DC inputvoltage-½ DC input voltage) 2 First Third DC input voltage (S1a′, S2a′)(S3b′, S4b′) (DC input voltage-Zero) 3 Second Third ½ DC input voltage(S2a′, S3a′) (S3b′, S4b′) (DC input voltage-½ DC input voltage)The control circuit may configure the inverter 800 to traverse thesequences of states shown in TABLE 14 sequentially back-and-forth, asdescribed herein.

During a third period, the control circuit may modulate the switch banks816, 818 to toggle the output voltage of the inverter 800 again between1/26 of the DC input voltage and zero, for example, using the sequenceof TABLE 13. During a fourth period, the control circuit may modulatethe switch banks 816, 818 to toggle the output voltage of the inverter800 between zero and −½ of the DC input voltage. An example switchingsequence for doing so is provided by TABLE 15 below:

TABLE 15 First Bank Second Bank 816 State 818 State (Switches (SwitchesOutput Voltage Closed) Closed) (First Pole 808-Second Pole 811) 1 FirstFirst Zero (S1a′, S1a′) (S1b′, S2b′) (DC input voltage-DC input voltage)2 Second First −½ DC input voltage (S2a′, S3a′) (S1b′, S2b′) (½ DC inputvoltage-DC input voltage) 3 Second Second Zero (S2a′, S3a′) (S2b′, S3b′)(½ DC input voltage-½ DC input voltage) 4 Third Second −½ DC inputvoltage (S3a′, S4a′) (S2b′, S3b′) (Zero-½ DC input voltage) 5 ThirdThird Zero (S3a′, S4a′) (S3b′, S4b′) (Zero-Zero)The control circuit may configure the inverter 800 to traverse thesequences of states shown in TABLE 15 sequentially back-and-forth, asdescribed herein.

During a fifth period, the control circuit may modulate the switch banks816, 818 to toggle the output voltage of the inverter 800 between −½ ofthe DC input voltage and −DC input voltage. An example switchingsequence for doing so is provided by TABLE 16 below:

TABLE 16 First Bank 816 State Second Bank 818 (Switches State OutputVoltage Closed) (Switches Closed) (First Pole 808-Second Pole 811) 1Second First −½ DC input voltage (S2a′, S3a′) (S1b′, S2b′) (½ DC inputvoltage-DC input voltage) 2 Third First −DC input voltage (S3a′, S4a′)(S1b′, S2b′) (Zero-DC input voltage) 3 Third Second −½ DC input voltage(S3a′, S4a′) (S2b′, S3b′) (Zero-½ DC input voltage)The control circuit may configure the inverter 800 to traverse thesequences of states shown in TABLE 16 sequentially back-and-forth, asdescribed herein.

During a sixth period, the control circuit may modulate the switch banks816, 818 to toggle the output voltage of the inverter 800 again between−½ of the DC input voltage and zero, for example, as shown by TABLE 15.In some examples, the control circuit may implement the six periodsdescribed with respect to the inverter 800 to implement one cycle of anoutput waveform. The shape of the waveform may be modified, for example,by varying the length of the various periods. This waveform sequence,however, is just one way that the inverter 800 may be used. Any suitableswitching sequence may be used to achieve any suitable type of waveform,for example, while enjoying some or all of the benefits describedherein.

FIG. 12 is a diagram showing yet another example of an inverter 900 forconverting DC to AC. The inverter 900 may receive the DC input voltageat a DC bus comprising a positive DC rail 912 and a negative DC rail914. The inverter 900 may be incorporated into an inverter systemsimilar to the system 100 described herein with respect to FIG. 2. Forexample, switch banks 916, 918 of the inverter 900 may be controlled bya control circuit similar to the control circuit 114 described herein.Also, an output waveform of the inverter 900 may be provided to afilter, similar to the filter 116 described herein. The inverter 900comprises three capacitors C1″, C2″, C3″ and C4″. Each capacitor maydrop ¼ of the DC input voltage. A first switch bank 916 comprises eightswitches S1 a″, S2 a″, S3 a″, S4 a″, S5 a″, S6 a″, S7 a″ and S8 a″. Theswitches S1 a″, S2 a″, S3 a″, S4 a″, S5 a″, S6 a″, S7 a″ and S8 a″ maybe configurable to five different states, as indicated by TABLE 17below:

TABLE 17 State Switches Closed Voltage at First Pole 908 First S1a″,S2a″, S3a″, S4a″ DC input voltage Second S2a″, S3a″, S4a″, S5a″ ¾ DCinput voltage Third S3a″, S4a″, S5a″, S6a″ ½ DC input voltage FourthS4a″, S5a″, S6a″, S7a″ ¼ DC input voltage Fifth S5a″, S6a″, S7a″, S8a″Zero (negative DC rail)A second switch bank 918 also comprises eight switches S1 b″, S2 b″, S3b″, S4 b″, S5 b″, S6 b″, S7b″ and S8b″ configurable to five differentstates, indicated by TABLE 18 below:

TABLE 18 State Switches Closed Voltage at Second Pole 911 First S1b″,S2b″, S3b″, S4b″ DC input voltage Second S2b″, S3b″, S4b″, S5b″ ¾ DCinput voltage Third S3b″, S4b″, S5b″, S6b″ ½ DC input voltage FourthS4b″, S5b″, S6b″, S7b″ ¼ DC input voltage Fifth S5b″, S6b″, S7b″, S8b″Zero (negative DC rail)Accordingly, the inverter 800 may be configurable to nine differentlevels, indicated by TABLE 19:

TABLE 19 Output Level First Pole Switch Bank State(s) Second Pole SwitchBank State(s) DC input (1) First (First Pole 908 = DC input (1) Fifth(Second Pole 911 = Zero) voltage voltage) ¾ DC input (1) First (FirstPole 908 = DC input (1) Fourth (Second Pole 911 = ¼ DC voltage voltage)input voltage) (2) Second (First Pole 908 = ¾ DC (2) Fifth (Second Pole911 = Zero) input voltage) ½ DC input (1) First (First Pole 908 = DCinput (1) Third (Second Pole 911 = ½ DC voltage voltage) input voltage)(2) Second (First Pole 908 = ¾ DC (2) Fourth (Second Pole 911 = ¼ DCinput voltage) input voltage) (3) Third (First Pole 908 = ½ DC (3) Fifth(Second Pole 911 = Zero) input voltage) ¼ DC input (1) First (First Pole908 = DC input (1) Second (Second Pole 911 = ¾ DC voltage voltage) inputvoltage) (2) Second (First Pole 908 = ¾ DC (2) Third (Second Pole 911 =½ DC input voltage) input voltage) (3) Third (First Pole 908 = ½ DC (3)Fourth (Second Pole 911 = ¼ DC input voltage) input voltage) (4) Fourth(First Pole 908 = ¼ DC (4) Fifth (Second Pole 911 = Zero) input voltage)0 (negative (1) First (First Pole 908 = DC input (1) First (Second Pole911 = DC input rail of DC voltage) voltage) input (2) Second (First Pole908 = ¾ DC (2) Second (Second Pole 911 = ¾ DC voltage) input voltage)input voltage) (3) Third (First Pole 908 = ½) (3) Third (Second Pole 911= ½) (4) Fourth (First Pole 908 = ¼ DC (4) Fourth (Second Pole 911 = ¼DC input voltage) input voltage) (5) Fifth (First Pole 908 = Zero) (5)Fifth (Second Pole 911 = Zero) −¼ DC (1) Second (First Pole 908 = ¾ DC(1) First (Second Pole 911 = DC input input voltage input voltage)voltage) (2) Third (First Pole 908 = ½ DC (2) Second (Second Pole 911 =¾ DC input voltage) input voltage) (3) Fourth (First Pole 908 = ¼ DC (3)Third (Second Pole 911 = ½) input voltage) (4) Fourth (Second Pole 911 =¼ DC (4) Fifth (First Pole 908 = Zero) input voltage) −½ DC (1) Third(First Pole 908 = ½) (1) First (Second Pole 911 = DC input input voltage(2) Fourth (First Pole 908 = ¼ DC voltage) input voltage) (2) Second(Second Pole 911 = ¾ DC (3) Third (First Pole 908 = Zero) input voltage)(3) Third (Second Pole 911 = ½) −¾ DC (1) Fourth (First Pole 908 = ¼ DC(1) First (Second Pole 911 = DC input input voltage input voltage)voltage) (2) Fifth (First Pole 908 = Zero) (2) Second (Second Pole 911 =¾ DC input voltage) −DC input (1) Fifth (First Pole 908 = Zero) (1)First (Second Pole 911 = DC input voltage voltage)

Any suitable switching sequence may be utilized for the inverter 900.For example, during a first period, the control circuit may modulate theswitch banks 916, 918 to toggle the output of the inverter 900 betweenzero and ¼ of the DC input voltage. An example switching sequence fordoing so is provided by TABLE 20 below:

TABLE 20 First Bank 916 State Second Bank 918 State Output Voltage(Switches Closed) (Switches Closed) (First Pole 908-Second Pole 911) 1First First 0 Volts (S1a″, S2a″, S3a″, S4a″) (S1b″, S2b″, S3b″, (DCinput voltage-DC input S4b″) voltage) 2 First Second ¼ DC input voltage(S1a″, S2a″, S3a″, S4a″) (S2b″, S3b″, S4b″, (DC input voltage-¾ DC inputS5b″) voltage) 3 Second Second 0 Volts (S2a″, S3a″, S4a″, S5a″) (S2b″,S3b″, S4b″, (¾ DC input voltage-¾ DC S5b″) input voltage) 4 Second Third¼ DC input voltage (S2a″, S3a″, S4a″, S5a″) (S3b″, S4b″, S5b″, (¾ DCinput voltage-½ DC S6b″) input voltage) 5 Third Third 0 Volts (S3a″,S4a″, S5a″, S6a″) (S3b″, S4b″, S5b″, (½ DC input voltage-½ DC S6b″)input voltage) 6 Third Fourth ¼ DC input voltage (S3a″, S4a″, S5a″,S6a″) (S4b″, S5b″, S6b″, (½ DC input voltage-¼ DC S7b″) input voltage) 7Fourth Fourth 0 Volts (S4a″, S5a″, S6a″, S7a″) (S4b″, S5b″, S6b″, (¼ DCinput voltage-¼ DC S7b″) input voltage) 8 Fourth Fifth ¼ DC inputvoltage (S4a″, S5a″, S6a″, S7a″) (S5b″, S6b″, S7b″, (¼ DC inputvoltage-Zero) S8b″) 9 Fifth Fifth 0 Volts (S5a″, S6a″, S7a″, S8a″)(S5b″, S6b″, S7b″, (Zero-Zero) S8b″)As described herein with respect to the switching of the inverter 10,the control circuit may configure the inverter 900 to traverse thesequence of states shown in TABLE 20 sequentially back-and-forth.

During a second period, the control circuit may modulate the switchbanks 916, 918 to toggle the output voltage of the inverter 900 between¼ of the DC input voltage and ½ of the DC input voltage. An exampleswitching sequence for doing so is provided by TABLE 21 below:

TABLE 21 First Bank 916 State Second Bank 918 State Output Voltage(Switches Closed) (Switches Closed) (First Pole 908-Second Pole 911) 1First Second ¼ DC input voltage (S1a″, S2a″, S3a″, S4a″) (S2b″, S3b″,S4b″, (DC input voltage-¾ DC input S5b″) voltage) 2 First Third ½ DCinput voltage (S1a″, S2a″, S3a″, S4a″) (S3b″, S4b″, S5b″, (DC inputvoltage-½ DC input S6b″) voltage) 3 Second Third ¼ DC input voltage(S2a″, S3a″, S4a″, S5a″) (S3b″, S4b″, S5b″, (¾ DC input voltage-½ DCS6b″) input voltage) 4 Second Fourth ½ DC input voltage (S2a″, S3a″,S4a″, S5a″) (S4b″, S5b″, S6b″, (¾ DC input voltage-¼ DC S7b″) inputvoltage) 5 Third Fourth ¼ DC input voltage (S3a″, S4a″, S5a″, S6a″)(S4b″, S5b″, S6b″, (½ DC input voltage-¼ DC S7b″) input voltage) 6 ThirdFifth ½ DC input voltage (S3a″, S4a″, S5a″, S6a″) (S5b″, S6b″, S7b″, (½DC input voltage-Zero) S8b″) 7 Fourth Fifth ¼ DC input voltage (S4a″,S5a″, S6a″, S7a″) (S5b″, S6b″, S7b″, (¼ DC input voltage-Zero) S8b″)As described herein with respect to the switching of the inverter 10,the control circuit may configure the inverter 900 to traverse thesequence of states shown in TABLE 21 sequentially back-and-forth.

During a third period, the control circuit may modulate the switch banks916, 918 to toggle the output voltage of the inverter 900 between ½ ofthe DC input voltage and ¾ of the DC input voltage. An example switchingsequence for doing so is provided by TABLE 22:

TABLE 22 First Bank 916 State Second Bank 918 State Output Voltage(Switches Closed) (Switches Closed) (First Pole 908-Second Pole 911) 1First Third ½ DC input voltage (S1a″, S2a″, S3a″, S4a″) (S3b″, S4b″,S5b″, (DC input voltage-½ DC input S6b″) voltage) 2 First Fourth ¾ DCinput voltage (S1a″, S2a″, S3a″, S4a″) (S4b″, S5b″, S6b″, (DC inputvoltage-¼ DC input S7b″) voltage) 3 Second Fourth ½ DC input voltage(S2a″, S3a″, S4a″, S5a″) (S4b″, S5b″, S6b″, (¾ DC input voltage-¼ DCS7b″) input voltage) 4 Second Fifth ¾ DC input voltage (S2a″, S3a″,S4a″, S5a″) (S5b″, S6b″, S7b″, ( 3/2 DC input voltage-Zero) S8b″) 5Third Fifth ½ DC input voltage (S3a″, S4a″, S5a″, S6a″) (S5b″, S6b″,S7b″, (½ DC input voltage-Zero) S8b″)As described herein with respect to the switching of the inverter 10,the control circuit may configure the inverter 900 to traverse thesequence of states shown in TABLE 22 sequentially back-and-forth.

During a fourth period, the control circuit may modulate the switchbanks 916, 918 to toggle the output voltage of the inverter 900 between¾ of the DC input voltage and the DC input voltage. An example switchingsequence for doing so is provided by TABLE 23 below:

TABLE 23 First Bank 916 State Second Bank 918 State Output Voltage(Switches Closed) (Switches Closed) (First Pole 908-Second Pole 911) 1First Fourth ¾ DC input voltage (S1a″, S2a″, S3a″, S4a″) (S4b″, S5b″,S6b″, (DC input voltage-¼ DC input S7b″) voltage) 2 First Fifth DC inputvoltage (S1a″, S2a″, S3a″, S4a″) (S5b″, S6b″, S7b″, (DC inputvoltage-Zero) S8b″) 3 Second Fifth ¾ DC input voltage (S2a″, S3a″, S4a″,S5a″) (S5b″, S6b″, S7b″, ( 3/2 DC input voltage-Zero) S8b″)As described herein with respect to the switching of the inverter 10,the control circuit may configure the inverter 900 to traverse thesequence of states shown in TABLE 23 sequentially back-and-forth.

During a fifth period, the control circuit may modulate the switch banks916, 918 to toggle the output voltage of the inverter 900 between ¾ ofthe DC input voltage and ½ of the DC input voltage, for example,according to the switching sequence of TABLE 22. During a sixth period,the control circuit may modulate the switch banks 916, 918 to toggle theoutput voltage of the inverter 900 between ½ of the DC input voltage and¼ of the DC input voltage, for example, according to the switchingsequence of TABLE 21. During a seventh period, the control circuit maymodulate the switch banks 916, 918 to toggle the output voltage of theinverter 900 between ½ of the DC input voltage and zero, for example,according to the switching sequence of TABLE 20. During an eighthperiod, the control circuit may modulate the switch banks 916, 918 totoggle the output voltage of the inverter 900 between zero and −¼ of theDC input voltage. An example switching sequence for doing so is providedby TABLE 24 below:

TABLE 24 First Bank 916 State Second Bank 918 State Output Voltage(Switches Closed) (Switches Closed) (First Pole 908-Second Pole 911) 1First First 0 Volts (S1a″, S2a″, S3a″, S4a″) (S1b″, S2b″, S3b″, (DCinput voltage-DC input S4b″) voltage) 2 Second First −¼ DC input voltage(S2a″, S3a″, S4a″, S5a″) (S1b″, S2b″, S3b″, (¾ DC input voltage-DC inputS4b″) voltage) 3 Second Second 0 Volts (S2a″, S3a″, S4a″, S5a″) (S2b″,S3b″, S4b″, (¾ DC input voltage-¾ DC S5b″) input voltage) 4 Third Second−¼ DC input voltage (S3a″, S4a″, S5a″, S6a″) (S2b″, S3b″, S4b″, (½ DCinput voltage-¾ DC S5b″) input voltage) 5 Third Third 0 Volts (S3a″,S4a″, S5a″, S6a″) (S3b″, S4b″, S5b″, (½ DC input voltage-½ DC S6b″)input voltage) 6 Fourth Third −¼ DC input voltage (S4a″, S5a″, S6a″,S7a″) (S3b″, S4b″, S5b″, (¼ DC input voltage-½ DC S6b″) input voltage) 7Fourth Fourth 0 Volts (S4a″, S5a″, S6a″, S7a″) (S4b″, S5b″, S6b″, (¼ DCinput voltage-¼ DC S7b″) input voltage) 8 Fifth Fourth −¼ DC inputvoltage (S5a″, S6a″, S7a″, S8a″) (S4b″, S5b″, S6b″, (Zero-¼ DC inputvoltage) S7b″) 9 Fifth Fifth 0 Volts (S5a″, S6a″, S7a″, S8a″) (S5b″,S6b″, S7b″, (Zero-Zero) S8b″)As described herein with respect to the switching of the inverter 10,the control circuit may configure the inverter 900 to traverse thesequence of states shown in TABLE 24 sequentially back-and-forth.

During a ninth period, the control circuit may modulate the switch banks916, 918 to toggle the output voltage of the inverter 900 between −¼ ofthe DC input voltage and −½ of the DC input voltage. An exampleswitching sequence for doing so is provided by TABLE 25 below:

TABLE 25 First Bank 916 State Second Bank 918 State Output Voltage(Switches Closed) (Switches Closed) (First Pole 908-Second Pole 911) 1Second First −¼ DC input voltage (S2a″, S3a″, S4a″, S5a″) (S1b″, S2b″,S3b″, (¾ DC input voltage-DC input S4b″) voltage) 2 Third First −½ DCinput voltage (S3a″, S4a″, S5a″, S6a″) (S1b″, S2b″, S3b″, (½ inputvoltage-DC input S4b″) voltage) 3 Third Second −¼ DC input voltage(S3a″, S4a″, S5a″, S6a″) (S2b″, S3b″, S4b″, (½ DC input voltage-¾ DCS5b″) input voltage) 4 Fourth Second −½ Volts (S4a″, S5a″, S6a″, S7a″)(S2b″, S3b″, S4b″, (¼ DC input voltage-¾ DC S5b″) input voltage) 5Fourth Third −¼ DC input voltage (S4a″, S5a″, S6a″, S7a″) (S3b″, S4b″,S5b″, (¼ DC input voltage-½ DC S6b″) input voltage) 6 Fifth Third −½Volts (S5a″, S6a″, S7a″, S8a″) (S3b″, S4b″, S5b″, (Zero-½ DC inputvoltage) S6b″) 7 Fifth Fourth −¼ DC input voltage (S5a″, S6a″, S7a″,S8a″) (S4b″, S5b″, S6b″, (Zero-¼ DC input voltage) S7b″)The control circuit may configure the inverter 900 to traverse thesequences of states shown in TABLE 25 sequentially back-and-forth, asdescribed herein.

During a tenth period, the control circuit may modulate the switch banks916, 918 to toggle the output voltage of the inverter 900 between −½ and−¾ of the DC input voltage. An example switching sequence for doing sois provided by TABLE 26 below:

TABLE 26 First Bank 916 State Second Bank 918 State Output Voltage(Switches Closed) (Switches Closed) (First Pole 908-Second Pole 911) 1Third First −½ DC input voltage (S3a″, S4a″, S5a″, S6a″) (S1b″, S2b″,S3b″, (½ input voltage-DC input S4b″) voltage) 2 Fourth First −¾ DCinput voltage (S4a″, S5a″, S6a″, S7a″) (S1b″, S2b″, S3b″, (¼ DC inputvoltage-DC input S4b″) voltage) 3 Fourth Second −½ Volts (S4a″, S5a″,S6a″, S7a″) (S2b″, S3b″, S4b″, (¼ DC input voltage-¾ DC S5b″) inputvoltage) 4 Fifth Second −¾ DC input voltage (S5a″, S6a″, S7a″, S8a″)(S2b″, S3b″, S4b″, (Zero-¾ DC input voltage) S5b″) 5 Fifth Third −½Volts (S5a″, S6a″, S7a″, S8a″) (S3b″, S4b″, S5b″, (Zero-½ DC inputvoltage) S6b″)The control circuit may configure the inverter 900 to traverse thesequences of states shown in TABLE 26 sequentially back-and-forth, asdescribed herein.

During an eleventh period, the control circuit may modulate the switchbanks 916, 918 to toggle the output voltage of the inverter 900 between−¾ of the DC input voltage and −1 of the DC input voltage. An exampleswitching sequence for doing so is provided by TABLE 27 below:

TABLE 27 First Bank 916 State Second Bank 918 State Output Voltage(Switches Closed) (Switches Closed) (First Pole 908-Second Pole 911) 1Fourth First −¾ DC input voltage (S4a″, S5a″, S6a″, S7a″) (S1b″, S2b″,S3b″, (¼ DC input voltage-DC input S4b″) voltage) 2 Fifth First − DCinput voltage Volts (S5a″, S6a″, S7a″, S8a″) (S1b″, S2b″, S3b″, (Zero-DCinput voltage) S4b″) 3 Fifth Second −¾ DC input voltage (S5a″, S6a″,S7a″, S8a″) (S2b″, S3b″, S4b″, (Zero-¾ DC input voltage) S5b″)The control circuit may configure the inverter 900 to traverse thesequences of states shown in TABLE 27 sequentially back-and-forth, asdescribed herein. During a twelfth period, the control circuit maymodulate the switch banks 916, 918 to toggle the output voltage of theinverter 900 between −¾ and −½ of the DC input voltage, for example,according to the switching sequence of TABLE 26. During a thirteenthperiod, the control circuit may modulate the switch banks 916, 918 totoggle the output voltage of the inverter 900 between −½ and −¼ of theDC input voltage, for example, according to the switching sequence ofTABLE 25. During a fourteenth period, the control circuit may modulatethe switch banks 916, 918 to toggle the output voltage of the inverter900 between ¼ of the DC input voltage and zero. In some examples, thecontrol circuit may implement the fourteen periods described withrespect to the inverter 900 to implement one cycle of an outputwaveform. The shape of the waveform may be modified, for example, byvarying the length of the various periods. This waveform sequence,however, is just one way that the inverter 900 may be used. Any suitableswitching sequence may be used to achieve any suitable type of waveform,for example, while enjoying some or all of the benefits describedherein. In various examples, other similar inverters may be generatedcomprising switching banks, poles and capacitors, as described herein.For example, inverters utilizing more than four capacitors could also beused.

In the switching sequence examples described with respect to TABLES 4-6for the inverter 10, TABLES 13-16 for the inverter 800 and TABLES 20-27for the inverter 900, the first and second switching banks are bothswitched during each period. For example, referring to TABLE 4, duringthe first period, the control circuit 114 toggles both the first switchbank 16 and the second switch bank 18. In some examples, however, thecontrol circuit 114 may be programmed to generate an output waveform byholding one switch bank constant while toggling the other switch bank.For example, FIGS. 13-14 show an alternate switching sequence that maybe used in conjunction with the inverter 100 to generate an outputwaveform 1050. FIG. 13 shows a diagram 1002 indicating the states ofswitches S1 a, S2 a, S3 a, S4 a, S5 a, S6 a of the first switch bank 16.FIG. 14 shows a diagram 1004 indicating the states of the switches S1 b,S2 b, S3 b, S4 b, S5 b, S6 b of the second switch bank 18. In thediagrams 1002, 1004, a “1” for a switch indicates that the switch isclosed, while a “0” for a switch indicates that the switch is open. FIG.15 is a diagram showing an output waveform generated in accordance withthe switching sequence of FIGS. 12-13. Although the switching sequenceof FIGS. 13-15 is described with respect to the inverter 10, similarswitching sequences may be used with the other inverters 800, 900described herein.

In the example of FIGS. 13-15, the DC input voltage is 450 Volts. Duringa first period 1004 between zero and about 1 millisecond (ms), theoutput of the inverter 100 (e.g., the waveform 1050) toggles betweenzero and 150 Volts, or ⅓ of the DC input voltage. During the firstperiod 1004, as shown in FIG. 13, the control circuit 114 may maintainthe first switch bank 16 is in its first state, with switches S1 a, S2a, and S3 a closed. Accordingly, the first pole 8 is at the DC inputvoltage (e.g.,450 Volts). Also during the first period 1004, as shown inFIG. 13, the control circuit 114 may toggle the second switch bankbetween the first state, with switches S1 b, S2 b, and S3 b closed andthe second state, with switches S2 b, S3 b, and S4 b closed. This causesthe voltage at the second pole 11 to toggle between the DC input voltage(e.g., 450 V) and ⅔ of the DC input voltage (e.g., 300 V). Thedifference between the poles 8, 11, then toggles between zero and 150 V,as indicated in the waveform 1050.

During a second period 1006 between about 1 ms and 2 ms, the controlcircuit 114 maintains the first switch bank 16 in the first state,maintaining the first pole 8 at the DC input voltage (e.g., 450 V). Thecontrol circuit 114 toggles the second switch bank 18 between the secondstage (S2 b, S3 b, S4 b closed) and the third state (S3 b, S4 b, S5 bclosed). This may toggle the voltage at the pole 11 between ⅓ of the DCinput voltage (e.g., 150 V) and ⅔ of the DC input voltage (300 V).Accordingly, the output waveform 1050 may toggle between about ⅓ of theDC input voltage (e.g., 150 V) and ⅔ of the DC input voltage (e.g.300V).

During a third period 1008 between about 2 ms and 4 ms, the controlcircuit 114 may continue to maintain the first switch bank 16 in thefirst state, maintaining the first pole 8 at the DC input voltage (e.g.,450 V). The control circuit 114 toggles the second switch bank 18between the third stage (S3 b, S4 b, S5 b closed) and the fourth state(S4 b, S5 b, S6 b closed). This may toggle the voltage at the pole 11between ⅓ of the DC input voltage (e.g. 150 V) and zero. With the firstpole 8 held at 450 V, this may cause the output waveform 1050 to togglebetween about ⅔ of the DC input voltage (e.g., 300 V) and the DC inputvoltage (e.g., 450 V).

During a fourth period 1010 between about 4 ms and 6 ms, the controlcircuit 114 may maintain the second switch bank 18 in the fourth state(S4 b, S5 b, S6 b closed), causing the second pole 11 to stay at zero.The control circuit 114 may also toggle the first switch bank 16 betweenthe first state (S1 a, S2 a, S3 a closed) and the second state (S2 a, S3a, S4 a closed), causing the voltage at the first pole 8 to togglebetween the DC input voltage (e.g., 450 V) and ⅔ of the DC input voltage(e.g., 300 V). As the second pole 11 is held at zero, this may reflectthe stat of the output waveform 1050 during the fourth period 1010.

During a fifth period 1012 between about 6 ms and 7.5 ms, the controlcircuit 114 may maintain the second switch bank 16 in the fourth state(S4 b, S5 b, S6 b closed), similar to the fourth period 1010. Thecontrol circuit 114 may toggle the first switch bank 16 between thesecond state (S2 a, S3 a, S4 a closed) and the third state (S3 a, S4 a,S5 a closed). This may toggle the first pole 8 between ⅔ of the DC inputvoltage (e.g., 300 V) and ⅓ of the DC input voltage (e.g., 150 V).Again, because the second pole 11 is held at zero, the output waveform1050 may also toggle between ⅔ of the DC input voltage (e.g., 300 V) and⅓ of the DC input voltage (e.g., 150 V).

During a sixth period 1014 between about 7.5 ms and 8.5 ms, the controlcircuit 114 may continue to maintain the second switch bank 16 in thefourth state (S4 b, S5 b, S6 b closed), drawing the pole 11 to zero. Thecontrol circuit 114 may toggle the first switch bank 16 between thethird state (S3 a, S4 a, S5 a closed) and the fourth state (S4 a, S5 a,S6 a closed), thus toggling the first pole 8 and the output waveform1050 between ½ of the DC input voltage (e.g. 150 V) and zero.

During a seventh period 1016 between about 8.5 ms and 9.5 ms, thecontrol circuit 114 may maintain the first switch bank 16 in the fourthstate (S4 a, S5 a, S6 a closed), drawing the pole 8 to zero. The controlcircuit 114 may toggle the second switch bank 18 between the third state(S3 b, S4 b, S5 b closed) and the fourth state (S4 b, S5 b, S6 bclosed), toggling the second pole 11 between ⅓ of the DC input voltage(e.g., 150 V) and zero. Because the first pole 8 is at zero, this maytoggle the output waveform 1050 between zero and −⅓ of the DC inputvoltage (e.g., −150 V).

During an eighth period 1018 between about 9.5 ms and 10.5 ms, thecontrol circuit 114 may maintain the first switch bank 16 in the fourthstate (S4 a, S5 a, S6 a closed), drawing the pole 8 to zero. The controlcircuit 114 may toggle the second switch bank 18 between the secondstate (S2 b, S3 b, S4 b closed) and the third state (S3 b, S4 b, S5 bclosed), toggling the second pole 11 between ⅔ of the DC input voltage(e.g., 300 V) and ⅓ of the DC input voltage (e.g., 150 V). Because thefirst pole 8 is at zero, this may toggle the output waveform between −⅓of the DC input voltage (e.g., −150 V) and −⅔ of the DC input voltage(e.g., −300 V).

During a ninth period 1020 between about 10.5 ms and 12.5 ms, thecontrol circuit 114 may maintain the first switch bank 16 in the fourthstate (S4 a, S5 a, S6 a closed), drawing the pole 8 to zero. The controlcircuit 114 may toggle the second switch bank 18 between the first state(S1 b, S2 b, S3 b closed) and the second state (S2 b, S3 b, S4 bclosed), toggling the second pole 11 between ⅔ of the DC input voltage(e.g., 300 V) and −1 of the DC input voltage (e.g., −450 V). Because thefirst pole 8 is zero, this may toggle the output waveform between −⅔ ofthe DC input voltage (e.g., −300 V) and −1 of the DC input voltage(e.g., −450 V).

During a tenth period 1022 between about 12.5 ms and 14.5 ms, thecontrol circuit 114 may maintain the second switch bank in the firststate (S1 b, S2 b, S3 b closed), drawing the pole 11 to the DC inputvoltage (e.g., 450 V). The control circuit 114 may toggle the firstswitch bank 16 between the third state (S3 a, S4 a, S5 a closed) and thefourth state (S4 a, S5 a, S6 a closed), toggling the first pole 8between ⅓ of the DC input voltage (e.g., 150 V) and zero. Because thesecond pole 11 is held at the DC input voltage (e.g., 450 V), this maycause the output waveform 1050 to toggle between −⅔ of the DC inputvoltage (−300 V) and −1 of the DC input voltage (−450 V).

During an eleventh period 1024 between about 14.5 ms and 15.5 ms, thecontrol circuit 114 may maintain the second switch bank in the firststate (S1 b, S2 b, S3 b closed), drawing the pole 11 to the DC inputvoltage (e.g., 450 V). The control circuit 114 may toggle the firstswitch bank 16 between the second state (S2 a, S3 a, S4 a closed) andthe third state (S3 a, S4 a, S5 a closed), toggling the first pole 8between ⅔ of the DC input voltage (e.g., 300 V) and ⅓ of the DC inputvoltage (e.g., 150 V). Because the second pole 11 is held at the DCinput voltage (e.g., 450 V), this may cause the output waveform 1050 totoggle between −⅓ of the DC input voltage (e.g., −150 V) and −⅔ of theDC input voltage (−300 V).

During a twelfth period 1026 between about 15.5 ms and 16.5 ms, thecontrol circuit 114 may maintain the second switch bank in the firststate (S1 b, S2 b, S3 b closed), drawing the pole 11 to the DC inputvoltage (e.g., 450 V). The control circuit 114 may toggle the firstswitch bank 16 between the first state (S1 a, S2 a, S3 a closed) and thesecond state (S2 a, S3 a, S4 a closed), toggling the first pole 8between ⅔ of the DC input voltage (e.g., 300 V) and the DC input voltage(e.g., 450 V). Because the second pole 11 is held at the DC inputvoltage (e.g., 450V), this may cause the output waveform 1050 to togglebetween −⅓ of the DC input voltage (e.g., −150 V) and zero. The twelvetime periods 1004, 1006, 1008, 1010, 1012, 1014, 1016, 1018, 1020, 1022,1024, 1026 may complete one cycle of the output waveform 1050. Thelengths of the respective periods may vary, for example, to vary theshape of the waveform 1050. Additional periods 1028, 1030, 1032 maycorrespond to a next cycle of the waveform 1050. For example, duringperiod 1028, the switch banks 16, 18 may be configured as described withrespect to the period 1004. Similarly, period 1030 may correspond toperiod 1006 and period 1032 may correspond to period 1008.

Although various systems described herein may be embodied in software orcode executed by one or more microprocessors as discussed above, as analternate the same may also be embodied in dedicated hardware or acombination of software/general purpose hardware and dedicated hardware.If embodied in dedicated hardware, each can be implemented as a circuitor state machine that employs any one of or a combination of a number oftechnologies. These technologies may include, but are not limited to,discrete logic circuits having logic gates for implementing variouslogic functions upon an application of one or more data signals,application specific integrated circuits having appropriate logic gates,or other components, etc. Such technologies are generally well known bythose of ordinary skill in the art and consequently, are not describedin detail herein.

The flowcharts and methods described herein show the functionality andoperation of various implementations. If embodied in software, eachblock or step may represent a module, segment, or portion of code thatcomprises program instructions to implement the specified logicalfunction(s). The program instructions may be embodied in the form ofsource code that comprises human-readable statements written in aprogramming language or machine code that comprises numericalinstructions recognizable by a suitable execution system such as aprocessing component in a computer system. If embodied in hardware, eachblock may represent a circuit or a number of interconnected circuits toimplement the specified logical function(s).

Although the flowcharts and methods described herein may describe aspecific order of execution, it is understood that the order ofexecution may differ from that which is described. For example, theorder of execution of two or more blocks or steps may be scrambledrelative to the order described. Also, two or more blocks or steps maybe executed concurrently or with partial concurrence. Further, in someembodiments, one or more of the blocks or steps may be skipped oromitted. It is understood that all such variations are within the scopeof the present disclosure.

Also, any logic or application described herein that comprises softwareor code can be embodied in any non-transitory computer readable mediumfor use by or in connection with an instruction execution system such asa processing component in a computer system. In this sense, the logicmay comprise, for example, statements including instructions anddeclarations that can be fetched from the computer readable medium andexecuted by the instruction execution system. In the context of thepresent disclosure, a “computer readable medium” can be any medium thatcan contain, store, or maintain the logic or application describedherein for use by or in connection with the instruction executionsystem. The computer readable medium can comprise any one of manyphysical media such as magnetic, optical, or semiconductor media. Morespecific examples of a suitable computer readable media include, but arenot limited to, magnetic tapes, magnetic floppy diskettes, magnetic harddrives, memory cards, solid-state drives, USB flash drives, or opticaldiscs. Also, the computer readable medium may be a random access memory(RAM) including, for example, static random access memory (SRAM) anddynamic random access memory (DRAM), or magnetic random access memory(MRAM). In addition, the computer readable medium may be a read-onlymemory (ROM), a programmable read-only memory (PROM), an erasableprogrammable read-only memory (EPROM), an electrically erasableprogrammable read-only memory (EEPROM), or other type of memory device.

It should be emphasized that the above-described embodiments of thepresent disclosure are merely possible examples of implementations setforth for a clear understanding of the principles of the disclosure.Many variations and modifications may be made to the above-describedexample(s) without departing substantially from the spirit andprinciples of the disclosure. All such modifications and variations areintended to be included herein within the scope of this disclosure andprotected by the following claims.

What is claimed is:
 1. A system for converting direct current (DC) toalternating current (AC), the system comprising: a DC bus comprising apositive DC rail and a negative DC rail to receive a DC input voltage; afirst capacitor comprising a first terminal electrically coupled to thepositive DC rail and a second terminal; a second capacitor comprising afirst terminal electrically coupled to the second terminal of the firstcapacitor and a second terminal; a third capacitor comprising a firstterminal electrically coupled to the second terminal of the secondcapacitor and a second terminal electrically coupled to the negative DCrail; a first pole switch bank comprising: a first switch comprising afirst terminal electrically coupled to the first terminal of thepositive DC rail and a second terminal; a second switch comprising afirst terminal electrically coupled to the second terminal of the firstswitch and a second terminal; a third switch comprising a first terminalelectrically coupled second terminal of the second switch and a secondterminal; a fourth switch comprising a first terminal electricallycoupled to the second terminal of the third switch and a secondterminal; a fifth switch comprising a first terminal electricallycoupled to the second terminal of the fourth switch and a secondterminal; a sixth switch comprising a first terminal electricallycoupled to the second terminal of the fifth switch and a second terminalelectrically coupled to the negative DC rail; a first diode comprising acathode electrically coupled to the second terminal of the first switchand an anode electrically coupled to the second terminal of the firstcapacitor; a second diode comprising a cathode electrically coupled tothe anode of the first diode and a cathode electrically coupled to thesecond terminal of the fourth switch; a third diode comprising a cathodeelectrically coupled to the second terminal of the second switch; and afourth diode comprising a cathode electrically coupled to the anode ofthe third diode and a cathode electrically coupled to the secondterminal of the fifth switch; a first pole coupled to the secondterminal of the fourth switch; and a control circuit configured toswitch the first switch, the second switch, the third switch, the fourthswitch, the fifth switch, and the sixth switch to provide an output ACsignal at the first pole.
 2. The system of claim 1, wherein the controlcircuit is further programmed to alternately switch the first poleswitch bank to: a first state where the first switch, the second switch,and the third switch are closed and the fourth switch, the fifth switchand the sixth switch are open; a second state where the second switch,the third switch, and the fourth switch are closed and the first switch,the fifth switch and the sixth switch are open; a third state where thethird switch, the fourth switch, and the fifth switch are closed and thefirst switch, the second switch, and the sixth switch are open; and afourth state where the fourth switch, the fifth switch, and the sixthswitch are closed and the first switch, the second switch, and the thirdswitch are open.
 3. The system of claim 2, wherein: when the first poleswitch bank is in the first state, a voltage of the first pole relativeto the negative DC rail is equal to the input DC voltage; when the firstpole switch bank is in the second state, the voltage of the first polerelative to the negative DC rail is about two-thirds of the input DCvoltage; when the first pole switch bank is in the third state, thevoltage of the first pole relative to the negative DC rail is aboutone-third of the input DC voltage; and when the first pole switch bankis in the fourth state, the voltage of the first pole relative to thenegative DC rail is about zero.
 4. The system of claim 3, furthercomprising a second pole switch bank, the second pole switch bankcomprising: a seventh switch comprising a first terminal electricallycoupled to the first terminal of the positive DC rail and a secondterminal; an eighth switch comprising a first terminal electricallycoupled to the second terminal of the seventh switch and a secondterminal; a ninth switch comprising a first terminal electricallycoupled second terminal of the eighth switch and a second terminal; atenth switch comprising a first terminal electrically coupled to thesecond terminal of the ninth switch and a second terminal; an eleventhswitch comprising a first terminal electrically coupled to the secondterminal of the tenth switch and a second terminal; a twelfth switchcomprising a first terminal electrically coupled to the second terminalof the eleventh switch and a second terminal electrically coupled to thenegative DC rail; a fifth diode comprising a cathode electricallycoupled to the second terminal of the seventh switch and an anodeelectrically coupled to the second terminal of the first capacitor; asixth diode comprising a cathode electrically coupled to the anode ofthe fifth diode and a cathode electrically coupled to the secondterminal of the tenth switch; a seventh diode comprising a cathodeelectrically coupled to the second terminal of the eighth switch; and aneighth diode comprising a cathode electrically coupled to the anode ofthe sixth diode and a cathode electrically coupled to the secondterminal of the twelfth switch.
 5. A system for converting directcurrent (DC) to alternating current (AC), the system comprising: a DCbus comprising a positive DC rail and a negative DC rail to receive a DCinput voltage; a first capacitor electrically coupled to the positive DCrail; a second capacitor, wherein the first capacitor, the secondcapacitor are electrically coupled in series between the positive DCrail and the negative DC rail; a first pole switch bank comprising aplurality of first pole switches; a first pole electrically coupled tothe first pole switch bank; and a control circuit comprising at leastone processor programmed to alternately switch the first pole switchbank to: a first state of the first pole switch bank in which the firstpole is electrically coupled to the positive DC rail; a second state ofthe first pole switch bank in which the first pole is electricallycoupled between the first capacitor and the second capacitor; and athird state of the first pole switch bank in which the first pole iselectrically coupled to the negative DC rail.
 6. The system of claim 5,further comprising a third capacitor electrically coupled to thenegative DC rail, wherein the first capacitor, the second capacitor andthe third capacitor are electrically coupled in series between thepositive DC rail and the negative DC rail, wherein the at least oneprocessor is further programmed to switch the first pole switch bank toa fourth state of the first pole switch bank in which the first pole iselectrically coupled between the second capacitor and the thirdcapacitor.
 7. The system of claim 6, further comprising: a second poleswitch bank comprising a plurality of second pole switches; and a secondpole electrically coupled to the second pole switch bank, wherein thecontrol circuit is further programmed to alternately switch the secondpole switch bank to: a first state of the second pole switch bank inwhich the second pole is electrically coupled to the positive DC rail; asecond state of the second pole switch bank in which the second pole iselectrically coupled between the first capacitor and the secondcapacitor; a third state of the second pole switch bank in which thesecond pole is electrically coupled between the second capacitor and thethird capacitor; and a fourth state of the second pole switch bank inwhich the second pole is electrically coupled to the negative DC rail.8. The system of claim 7, wherein the control circuit is furtherprogrammed to: during a first period, cycle the first pole switch bankand the second pole switch bank sequentially bank-and-forth between: (a)the first pole switch bank being in the first state of the first poleswitch bank and the second pole switch bank being in the third state ofthe second pole switch bank; (b) the first pole switch bank being in thefirst state of the first pole switch bank and the second pole switchbank being in the fourth state of the second pole switch bank; and (c)the first pole switch bank being in the second state of the first poleswitch bank and the second pole switch bank being in the fourth state ofthe second pole switch bank.
 9. The system of claim 8, wherein thecontrol circuit is further programmed to cycle the first pole switchbank sequentially back-and-forth at a switching frequency of about 10kHz.
 10. The system of claim 8, wherein the control circuit is furtherprogrammed to: during a second period after the first period, cycle thefirst pole switch bank and the second pole switch bank sequentiallyback-and-forth between: (a) the first pole switch bank being in thefirst state of the first pole switch bank and the second pole switchbank being in the second state of the second pole switch bank; (b) thefirst pole switch bank being in the first state of the first pole switchbank and the second pole switch bank being in the third state of thesecond pole switch bank; (c) the first pole switch bank being in thesecond state of the first pole switch bank and the second pole switchbank being in the third state of the second pole switch bank; (d) thefirst pole switch bank being in the second state of the first poleswitch bank and the second pole switch bank being in the fourth state ofthe second pole switch bank; and (e) the first pole switch bank being inthe third state of the first pole switch bank and the second pole switchbank being in the fourth state of the second pole switch bank.
 11. Thesystem of claim 10, wherein the control circuit is further programmedto: during a third period after the second period, cycle the first poleswitch bank and the second pole switch bank sequentially back-and-forthbetween: (a) the first pole switch bank being in the first state of thefirst pole switch bank and the second pole switch bank being in thefirst state of the second pole switch bank; (b) the first pole switchbank being in the first state of the first pole switch bank and thesecond pole switch bank being in the second state of the second poleswitch bank; (c) the first pole switch bank being in the second state ofthe first pole switch bank and the second pole switch bank being in thesecond state of the second pole switch bank; (d) the first pole switchbank being in the second state of the first pole switch bank and thesecond pole switch bank being in the third state of the second poleswitch bank; (e) the first pole switch bank being in the third state ofthe first pole switch bank and the second pole switch bank being in thethird state of the second pole switch bank; (f) the first pole switchbank being in the third state of the first pole switch bank and thesecond pole switch bank being in the fourth state of the second poleswitch bank; and (g) the first pole switch bank being in the fourthstate of the first pole switch bank and the second pole switch bankbeing in the fourth state of the second pole switch bank.
 12. The systemof claim 11, wherein the control circuit is further programmed to:during a fourth period after the third period, cycle the first poleswitch bank and the second pole switch bank sequentially back-and-forthbetween: (a) the first pole switch bank being in the first state of thefirst pole switch bank and the second pole switch bank being in thefirst state of the second pole switch bank; (b) the first pole switchbank being in the second state of the first pole switch bank and thesecond pole switch bank being in the second state of the first poleswitch bank; (c) the first pole switch bank being in the second state ofthe first pole switch bank and the second pole switch bank being in thesecond state of the second pole switch bank; (d) the first pole switchbank being in the third state of the first pole switch bank and thesecond pole switch bank being in the second state of the second poleswitch bank; (e) the first pole switch bank being in the third state ofthe first pole switch bank and the second pole switch bank being in thethird state of the second pole switch bank; (f) the first pole switchbank being in the fourth state of the first pole switch bank and thesecond pole switch bank being in the third state of the second poleswitch bank; and (g) the first pole switch bank being in the fourthstate of the first pole switch bank and the second pole switch bankbeing in the fourth state of the second pole switch bank.
 13. The systemof claim 12, wherein the control circuit is further programmed to:during a fifth period after the fourth period, cycle the first poleswitch bank and the second pole switch bank sequentially back-and-forthbetween: (a) the first pole switch bank being in the second state of thefirst pole switch bank and the second pole switch bank being in thefirst state of the second pole switch bank; (b) the first pole switchbank being in the third state of the first pole switch bank and thesecond pole switch bank being in the first state of the second poleswitch bank; (c) the first pole switch bank being in the third state ofthe first pole switch bank and the second pole switch bank being in thesecond state of the second pole switch bank; (d) the first pole switchbank being in the fourth state of the first pole switch bank and thesecond pole switch bank being in the second state of the second poleswitch bank; and (e) the first pole switch bank being in the fourthstate of the first pole switch bank and the second pole switch bankbeing in the third state of the second pole switch bank.
 14. The systemof claim 13, wherein the control circuit is further programmed to:during a sixth period after the fifth period, cycle the first poleswitch bank and the second pole switch bank sequentially back-and-forthbetween: (a) the first pole switch bank being in the third state of thefirst pole switch bank and the second pole switch bank being in thefirst state of the second pole switch bank; (b) the first pole switchbank being in the fourth state of the first pole switch bank and thesecond pole switch bank being in the first state of the second poleswitch bank; and (c) the first pole switch bank being in the fourthstate of the first pole switch bank and the second pole switch bankbeing in the second state of the second pole switch bank.
 15. The systemof claim 7, wherein the control circuit is programmed to, during a firstperiod: switch the first pole switch bank to the first state of thefirst pole switch bank and the second pole switch bank to the thirdstate of the second pole switch bank; switch the second pole switch bankfrom the third state of the second pole switch bank to the fourth stateof the second pole switch bank; and switch the first pole switch bankfrom the first state of the first pole switch bank to the second stateof the second pole switch bank.
 16. The system of claim 15, wherein thecontrol circuit is further programmed to, during the first period:switch the first pole switch bank from the second state of the firstpole switch bank to the first state of the first pole switch bank; andswitch the second pole switch bank from the fourth state of the secondpole switch bank to the third state of the second pole switch bank. 17.The system of claim 15, wherein the control circuit is programmed to,during a second period after the first period: switch the first poleswitch bank to the first state of the first pole switch bank and thesecond pole switch bank to the second state of the second pole switchbank; and switch the second pole switch bank from the second state ofthe second pole switch bank to the third state of the second pole switchbank; switch the first pole switch bank from the first state of thesecond pole switch bank to the second state of the second pole switchbank; switch the second pole switch bank from the third state of thesecond pole switch bank to the fourth state of the second pole switchbank; and switch the first pole switch bank from the second state of thesecond pole switch bank to the third state of the second pole switchbank.
 18. The system of claim 5, further comprising a third capacitorelectrically coupled to the second capacitor and a fourth capacitorelectrically coupled between the third capacitor and the negative DCrail, wherein the first capacitor, the second capacitor, the thirdcapacitor and the fourth capacitor are electrically coupled in seriesbetween the positive DC rail and the negative DC rail, and wherein theat least one processor is further programmed to switch the first poleswitch bank to: a fourth state of the first pole switch bank in whichthe first pole is electrically coupled between the second capacitor andthe third capacitor; and a fifth state of the first pole switch bank inwhich the first pole is electrically coupled between the third capacitorand the fourth capacitor.
 19. A system for converting direct current(DC) to alternating current (AC), the system comprising: a DC buscomprising a positive DC rail and a negative DC rail to receive a DCinput voltage; a first capacitor electrically coupled to the positive DCrail; a second capacitor; a third capacitor electrically coupled to thenegative DC rail, wherein the first capacitor, the second capacitor andthe third capacitor are electrically coupled in series between thepositive DC rail and the negative DC rail; a first pole; means foralternately electrically coupling the first pole to: (a) the positive DCrail; (b) a position between the first capacitor and the secondcapacitor; or (c) the negative DC rail; a second pole; and means foralternately electrically coupling the second pole to: (a) the positiveDC rail; (b) the position between the first capacitor and the secondcapacitor; or (c) the negative DC rail.
 20. The system of claim 17,further comprising: a third capacitor electrically coupled between thesecond capacitor and the negative DC rail; and means for electricallycoupling the first pole to a position between the second capacitor andthe third capacitor; and means for electrically coupling the second poleto the position between the second capacitor and the third capacitor.21. The system of claim 20, further comprising means for, during a firstperiod, electrically coupling the first and second poles to cycle avoltage difference between the first and second poles between the DCinput voltage and ⅔ of the DC input voltage.
 22. The system of claim 21,further comprising means for, during a second period after the firstperiod, electrically coupling the first and second poles to cycle thevoltage difference between the first and second poles between ⅔ of theDC input voltage and ⅓ of the DC input voltage.
 23. The system of claim21, further comprising means for, during a third period after the secondperiod, electrically coupling the first and second poles to cycle thevoltage difference between the first and second poles between ⅓ of theDC input voltage and zero.